ADS58J63

Vignesh ravi

Part Number: ADS58J63

ZYNQ ZCU102 FPGA ADC(ADS58J63) EVM bring up is facing interfacing issues. The LMFS 4841 mode 0 configuration file provided by TI is not providing the required configuration. On loading the file in ADC GUI provided by TI, we are unable to obtain the option of setting 40x Mode, 4-Lanes/ADC as per our requirement under JESD PLL Mode drop-down menu in ADS54Jxx tab.

We tried manual configuration of ADC-JESD registers by creating a configuration file, according to the ADS58J63 user guide. On loading the same configuration file multiple times, we obtained different ADC outputs each time. Also, instead of getting bcbc... sequence as per K28.5 character set, we observed some other random sequence on each lane.

Kindly assist us in resolving this configuration issue. Looking forward to hearing from you.

PFA screenshots of ADS54Jxx GUI v1.8.

4426.Address 6a0016.docx

over 5 years ago

0 Ebenezer Dwobeng over 5 years ago

TI__Genius 9695 points

Hi Vignesh,

I am looking into this.

Thanks

0 Vignesh ravi over 5 years ago in reply to Ebenezer Dwobeng

Prodigy 90 points

Hi Ebenezer Dwobeng,

Cloud you help me ASAP. Any new revision document for ADS58J63 because I was found the modification done in the JESD PLL Mode. Could you share the Mode 0 LMFS 4841 configuration file for ADS58J63 EVM.

0 Ebenezer Dwobeng over 5 years ago in reply to Vignesh ravi

TI__Genius 9695 points

Hi Vignesh,

This is a quad channel device so there are 4 ADCs in each die. In LMF = 484 mode, each ADC uses 1 lane to transmit data as shown below.

4lanes/ADC will mean a total of 16lanes which is not supported by this device. After loading the config file for LMF=484 mode, you do not have to make any changes to the JESD204B interface in the GUI because the device will already be configured correctly

Thanks,

Eben.

0 Vignesh ravi over 5 years ago in reply to Ebenezer Dwobeng

Prodigy 90 points

Hi Ebenezer,

1) Yes, we also require one lane per ADC.

2)After uploading the Mode 0 config file, it does not shows LMFS 4841 option in JESD mode drop down menu in GUI as shown in figure.

3)Also, we require 40x mode,4lane/ADC but this option is not present in JESD PLL Mode drop down menu in GUI as shown in figure.

4)Select the device Tab is showing Incorrect part number.

5) After uploading Mode 0 config file without making any changes, following is the output we are receiving. As it can be seen, we are not obtaining bcbc.. sequence in any of the four lanes. bcbc.. sequence is requird by FPGA to assert JESD SYNC signal.

0 Ebenezer Dwobeng over 5 years ago in reply to Vignesh ravi

TI__Genius 9695 points

Hi Vignesh

2,3,4)The GUI was designed originally for a different device so not all options for ADS58J63 is available. But the config file will set the device in the correct mode although the GUI may not display correctly
5)Make sure to push the ADC hardware reset SW1 before loading the configuration file for mode 0.

Thanks,
Eben.

0 Vignesh ravi over 5 years ago in reply to Ebenezer Dwobeng

Prodigy 90 points

Hi Ebenezer,

1) Already pressed the reset before dumping the config file in the board.

2)We are configuring the ADC board as per ADC EVM document. Still, we are not getting the bcbc.. sequence in any of the four lanes.

0 Ebenezer Dwobeng over 5 years ago in reply to Vignesh ravi

TI__Genius 9695 points

Hi Vignesh,

It is possible the ADC is expecting the JESD204B syncb on the syncbcd input so duplicate the same syncb from FPGA to syncbab and syncbcd input pins.

I expect the ADC to transmit BCBC characters when SYNCB is pulled low.

Thanks,

Eben.

0 Vignesh ravi over 5 years ago in reply to Ebenezer Dwobeng

Prodigy 90 points

Hi Ebenezer,

Kindly elaborate the steps to make SYNCB signal pulled low? And whether it should be done in hardware or software.

0 Ebenezer Dwobeng over 5 years ago in reply to Vignesh ravi

TI__Genius 9695 points

Hi Vignesh,

SYNCB should be controlled automatically by state machines inside the JESD204B IP used in the FPGA. Normally, after reset of the JESD204B IP in FPGA, the following sequence of events are expected:
1) SYNCB is pulled low by FPGA
2) ADC responds to low SYNCB by transmitting BCBC chractecters
3)FPGA pulls SYNCB high after it successfully receives more than 4 BCBC characters
4)ADC responds to high SYNCB by starting ILAS sequence followed by data transmission
I suggest that you contact the FPGA vendor for support regarding why SYNCB is not pulled low.

Thanks,
Eben.