Hello all! I have board with FPGA + ADC32rf80 + LMK. I can receive synchronous ADC samples from channels A & B. I want to receive synchronous test patterns from both channels. Datasheet says: "The test patterns can be synchronized for both ADC channels using the SYSREF signal". But on practice i see different ramp counter in channels.
My steps:
1. Reset LMK over GPIO pin.
2. Initialization of LMK, SYSREF disabled.
3. Reset ADC over GPIO pin.
4. Initialization of ADC (I also setup the register 0x01E DDC DET LAT). Also i have setup test pattern = "ramp" (unique for I/Q mode)
5. Initialization of JESD interface in FPGA.
6. Enable SYSREF as aperiodic multi-shot pulses (Datasheet page 33, 8.3.3.1 Using SYSREF):
a) write to LMK SYSREF pulse command (1st SYSREF)
b) delay > 40 us
c) set MASK CLKDIV bit in ADC
d) write to LMK SYSREF pulse command (2nd SYSREF)
e) write to LMK SYSREF pulse command (3rd SYSREF)
f) set MASK NCO and LMFC counter bit in ADC
g) write to LMK SYSREF pulse command (4th SYSREF)
Can you advise something?
