Good day,
I have a design on an FPGA that includes two JEDS204B data receivers. The first receives data from channel A of the ADC32RF80 while the second receives data from channel B. When I configure the DDCs of channel A to Divide-by-8, LMFS=8821 and the DDCs of channel B to Divide-by-24, LMFS=4841, I only receive valid data on the second JESD204B data receiver.
During debugging I configured the DDCs of both ADC channels to Divide-by-8, LMFS=8821, and I received valid data on the first JESD204B data receiver. Also, after configuring the DDCs of both ADC channels to Divide-by-24, LMFS=4841, I received valid data on the second JESD204B data receiver. Thus, whenever the decimation settings of the ADC channels differ, I receive invalid data on one of the JESD204B receivers.
My question is: Does the ADC32RF80 allow different DDC settings for its two ADC channels?
Regards,
Francois Tolmie
