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Part Number: ADC32RF80
Tool/software: Code Composer Studio
We want to develop ADC32RF80, but there are too many registers.
Is there any reference code that can help us?
Can it be provided?
The start-up sequence (9.1.1) in the device datasheet (http://www.ti.com/lit/ds/symlink/adc32rf80.pdf) explains the steps to configure the device and referes to a folder (SBAA226). This folder contains the configuration files associated with the steps in the sequence. This should help you with the required register writes to configure the device in a specific mode.
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In reply to Satish Uppathil:
In reply to Jerry Hsueh:
Jerry: Is there a question/issue from your previous post? I do not follow it. --RJH
In reply to RJ Hopper:
Sorry, my questions is as follows.
Can you help provide the following register configuration?
From the picture I ascertained your requirement:
I do not agree with the serdes speed of 19.6608 Gbps as that is too fast for the device. Per the datasheet the mode corresponds to the one copied above.
You can use the ADC32RFxx GUI to test this mode and/or to download a configuration file. If you do not have the GUI, you can download it from the ADC32RF45EVM product page on TI.com.
When you first open the GUI you can go to the Quick Setup tab. Change the "Select the Device" menu to "ADC32RFxx". Then follow this sequence:
The program should auto-populate the LMFS 4421 configuration. From there you press "Program EVM". This will generate a config file that you can copy for your own system. For example, you can double-click the "Idle" name in the lower left window to open the status log where you can see all of the register writes happening.
Thank you for your kindly support.
I would like to ask the following table which contains all the register configurations of the clock chip and ADC.
I want to know if the chip can work properly if it is configurated in the order of tables in the process of configuring the chip.
No. There is an order required which the log file/config file supports. --RJH
But the configuration file is a copy of the form.There are many clock operations and status reads in the log file.I want a complete and concise configuration sequence that can be used for my own project.
In reply to jan joe:
I am a bit confused. The Low Level Tab displays the register address and data for the LMK clock chip and the ADC chip in a compartmentalized fashion to make it easy to read and understand. It is not possible to simply regurgitate the address/data from the low level page and get the device working. There is a proper sequence needed to establish the JESD link. Actions like turning on and off the LMK sysref are required actions to get the link established. There may also be some proprietary registers that are written for ADC trimming purposes that are not specifically called out in the Low Level Tab.
The GUI outputs a config file consistent with the mode of operation set-up from the front panel. This config file is intended for you to use in your project. The idea is that if it works for the EVM then it will work for your system. Of course, you may need to make minor modifications to support your product like changing the clock output ports to support your unique layout. The file is long and may seem like it is not optimized. There likely is some repetition that could be streamlined a bit, particularly related to opening and closing SPI pages. But for simplicity this level of optimization is not implemented in the config file.
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