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AFE7070 Dual input clock(00)
Part Number: AFE7070
I have a situation where I need to burst data into an AFE7070 from a microcontroller. I'm hoping to use Dual Input Clock Mode so that I can make use of the FIFO.
A few questions:
1. So long as I throttle using the alarm_SDO pin to avoid over-running the FIFO, can the CLK_IO be discontinuous, such that I only provide the CLK_IO when I have an I or Q data value that I want clocked into the FIFO?
2. How large is the FIFO? Please tell me if the number you quote me in I/Q pairs or in single (I or Q) entries?
3. Does the SYNC_SLEEP pin (when configured as SYNC) clear the FIFO pointers?
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In reply to Vijayendra Varma Siddamsetty:
In reply to Howard Del Fava1:
Here are the answers to my questions.
2. 8 samples deep. 14 bits wide.
3. SYNC will re-initialize the read and write pointers to their default position.
In reply to Yusuf%20Agoro:
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