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Part Number: ADS58J63
I see that in Page 80h, register address 53h, bit 7 - it says enable "Divide by 2" for proper operation of ADS58J63.
Does it mean that I have to supply 1GHz clock to operate ADC at 500MSPS? Please clarify.
The datasheet specification for the clock input range is 250MHz to 500MHz. (page 5 of the datasheet)
Also, as an example, if you look at the ADS58j63 EVM User's Guide, section 2.31,
It mentioned the LMK04828 on step 4 generating 491.52MHz of clock to the ADC. The ADC is operating in mode 0 with decimation by 2. Therefore, the output rate of the data converter after decimation is 250MSPS. I believe the divide by 2 clock divider option is necessary to generate the internal clocks needed for the decimation logic.
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