• Resolved

DAC38RF89: no output data / single tone

Prodigy 60 points

Replies: 11

Views: 193

Part Number: DAC38RF89

Hello!

I have a custom DAC38RF89 board with no JTAG available.

Here is my use conditions:

- dacclk=328MHz, PLL, interpolation=24

- single DAC, LMFS=22210, K=16

- JESD204b subclass 0 (sysref internally genereted)

For now, I have progress with JESD204b passing most of SerDes tests (PRBS-7/23/31) and link tests (k28.5, d21.5) according to lane alarms and sync status stable HIGH.

But when running in "non-test flow" there is no output data from DAC, I mean no data at all - no matter configured as normal operation or constant single tone (0x12F 0x0001 / 0x130 0x7FFF).

My config with actual reg data is in attachment.

Thanks!

Alex

dac38rf89.cfg)

  • Hi Alex,

    We are taking a look into this, and will be back with you soon.

    Best Regards,

    Dan

  • Guru 55430 points

    Alex,

    Is the DAC sample rate = 7872MSPS? This part will require at least 2 SYSREF pulses. How many are you generating?  Are you using the NCO? Do you have an option to run as subclass 1 just to verify you can get an output? Is the PLL locked? 

    Regards,

    Jim  

  • In reply to jim s:

    Jim,

    Thank you for reply!

    Here is asked info:
    - DAC sample rate=7872MSPS
    - have NCO
    - DAC PLL locked
    Additionally, I have SPI_CLK=0.7MHz, if it's important.

    I think running subclass 1 is not an option because there is a design error on board in SYSREF generation - SYSREF and DACCLK is generated by single group of LMK04816 and can have equal frequencies only.

    So I am running subclass 0 and using internal SYSREF generator like that:
    0x410 0x4
    0x410 0
    0x411 LCM(24, 4*16*2)=384
    0x410 0x1

    I am not sure in how internal SYSREF is truly generated, so I can not tell how many pulses generated.

  • Guru 55430 points

    In reply to Alexey Voinkov:

    DAC38RF89_LMF_2221_NCO_100MHz.cfgAlex,

    If your DACCLK is connected to the differential input pins, try the attached config file. This should provide a 100MHz output from CHA using only the NCO. This is a good test to verify your clock, power and SPI are working properly. If you are using the single-ended DCLK input, change register 0x431 from 0x400 to 0x2400 in the config file.

    Regards,

    Jim

  • In reply to jim s:

    Jim,

    Is 0x0000 value correct for 0x130 reg in that use case?
    Anyway, with both non-zero and zero values I still have nothing at my DAC output.

    At the same time I believe that my power is OK (provided according to datasheet, checked with voltmeter), DACCLK is OK (generated by LMK04816 and checked with spectrum analyser), SPI is OK too (using in 3 wire mod, have a plenty of time working with that SPI infrastructure with no trouble).

  • Guru 55430 points

    In reply to Alexey Voinkov:

    Alex,

    Can you send your schematic? Not sure why you are having an issue. It is pretty straight forward to get an NCO output tone with a minimum number of register settings.

    Regards,

    Jim

  • In reply to jim s:

    Jim,

    PDF schematic of my DAC38RF89 node is in attachment (including information about already fixed design errors).

    Extended materials info is available with component's drop-down list.

    Alex

    custom_board.zip

  • Guru 55430 points

    In reply to Alexey Voinkov:

    Alex,

    I could not open the file you sent. Can you just send these as pdf's?

    Regards,

    Jim

  • In reply to jim s:

    Jim,

    Here is PDF.

    Alex

    custom_board.pdf

  • Guru 55430 points

    In reply to Alexey Voinkov:

    Alex,

    Make sure you toggle the reset pin (K9) from high to low to high after clocks and power are applied. Make sure the sleep pin is low, and the TXENABLE pin is high. Otherwise, there will be no output. When checking for an output, probe C315 in case there is an issue with all of the other parts between this point and the SMA. Do you have an option to monitor the RFDAC1_CLKTX outputs? This is another test point that would verify the part is getting a proper clock. To enable this output, set the following registers as show:

    Page 4, address 0x0b data 0x20, and address 0x0C data 0x2F02.

    The CLKTX output will be  a divide by 4 of the DACCLK.

    Regards,

    Jim