I'm using the DAC38RF97 on a custom PCB with 20x interpolation.
Here are some details of the configuration:
100MHz reference clock (single ended)
DAC PLL output freq = 6400MHz (locks with an LF=3)
JESD mode: 42111
Interp: 20x
Lane rate: 3200 Mbps (SERDES PLL locks, rate =1/2)
Subclass 0
While the datasheet shows that 20x interpolation is supported, it appears that there are several apparent gaps in the documentation/tools, namely:
1) Table 36. Register Programming for JESD and Interpolation Mode has no entry for 20x in the 42111 mode. In fact, there is only one entry for 20x in the entire table (22210/44210). Can you provide an entry for 20x 42111?
2) Extrapolating from the other table entries, I presume that CLKJESD_DIV should be div40, however there is no entry in the register for div40 (0x125, 15:12). Is div40 correct? How do I program this? CLKJESD_OUT_DIV looks to be div160, which has an entry.
3) The 3p0 version of the EVM tool does not appear to allow 20x to be selected when 4 lanes are chosen, even if the DAC38RF97 is specifically chosen from the drop down box. Only 12x, 16x, 18x, and 24x show up in the drop down box when 4 lanes are chosen. Where is 20x?
4) I don't see a good description of what "Clock phases" (0x14a, bits 1:0) means (other than table 36, which just gives the value for the desired mode). What does "clock phases" mean?
Any chance you could provide a .cfg file for this configuration?
Thanks.
