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DAC38RF80: Is there any way to tell if the DAC has seen the required number of SYSREF edges in initialization

Part Number: DAC38RF80

Hello again,

The motivation for my question regarding the SYSREF capture circuit (which I still need to follow up on) is because we were having a failure in our system where we were not seeing RF output, and it seems like I was able to fix the behavior by adding a delay before turning off the SYSREF (the whole initialization sequence was given to me by an FPGA designer who doesn't work at my company anymore).

So, the heart of my question is this:  Is there anything I can do to ensure the various required 2 rising SYSREF edges are seen, as outlined in Figure 167 of the DAC38RF8x datasheet (text in red in the block AFTER that labeled "Start SYSREF Generation"), in the 4 separate steps listed there?  Is there a condition that can be checked by reading particular registers, for example?

Thanks again,

Matt