Part Number: ADS58J63
I am seeing that the JESD data for some lanes in ADC is received in reverse order by FPGA.
i.e. For some lanes the data is B15 - B0 and for some lanes it comes as B7-B0;B15-B8.
And this changes when I do a JESD reset.
i.e. the lane on which I am receiving bit in order B15-B0 can change to B7-B0;B15-B8 and vice versa.
The attached FPGA capture shows the bit packing order.ADS58J63-MSB1.cfg
In both cases JESD link is stable.
Please let me know why this behaviour can happen.
I have attached my ADC configuration for your reference. Below are main setting of the ADC.
ADC mode: Mode 0
Sampling rate: 500MHz
DDC: Yes, Fs/4
Let me know if you need any further information.
I apologize. But mistake I added same snapshot twice for FPGA data capture.
You can make out the LSB as the bit which is always '0'.
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In reply to Kiran VG:
When you mentioned JESD reset, which JESD IP are you resetting? Is it the FPGA JESD RX IP?
The JESD204 requirement states that the JESD204 TX (ADC) need to be up and running before the JESD204RX IP (FPGA). If you have them in reverse order, the JESD204 RX may not be receiving data properly. This is due to the JESD204 RX has all the smart for the hand-shake, and therefore need to be initialized at a later time.
I do not believe there are JESD reset on the ADS58J63 on the JESD204 IP itself. There are digital core reset available.
If you want to eliminate JESD204 IP on the ADC side, you may use test pattern feature on the 0x0F register of the ADC page, and send out a ramp pattern to double check the validity from the data at the DDC side (before JESD204 TX IP)
In reply to Kang Hsia:
By JESD reset, I meant FPGA JESD RX IP reset.
My sequence of operation is a below.
1. FPGA board is configured. But FPGA JESD RX IP is held at reset.
2. ADC board is configured.
3. I can see FPGA receiving "bcbc" characters on JESD lanes. But FPGA JESD RX IP is still in reset.
4. I then bring the FPGA JESD RX IP out of reset.
5. I see that JESD links are established and FPGA starts receiving data from ADC.
Since I am keeping FPGA JESD RX IP in reset until ADCs are configured and then establishing the links, I believe the order of configuring the devices is fine. Please let me know if I need to change the order.
Yes, this is a correct order.
If your FPGA need some sort of SerDes level training before JESD204 link establishment, you may consider the following PRBS based test pattern with scrambling enabled.
You may initially issue a logical SYNCout from the FPGA from logic HI -> LOW -> HI to create a "dummy" link establishment signal so the ADC can send out the necessary PRBS pattern for your SerDes receiver training. Then you can reset the JESD204B IP core on the FPGA side to issue can actual link establishment setup, and disable the PRBS pattern to start the actual ADC data traffic.
Hi Kang Hsia,
Thanks for the update. I'll try to do this and check.
In the meantime can you review the configuration and let me know if there are any issues in ADC configuration. I have attached the same here for your reference.
Basic configuration settings are as below:
JESD Mode: Mode 0
Nyquist zone 2
Please try the attached configuration file. These are the only register writes required to get the TI EVM running using your settings. Make sure to give the part a hard reset after clocks are applied and before writing these register values.
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