Part Number: DAC38RF89
My customer wants to do a PRBS31 test, by using the checker in DAC38RF89 to check if the physical layer is good.
They can make the DAC38RF89 work well if FPGA output tone.
But they don't know how to allocate the PRBS31 data into the 8 lane of JESD204b.
From this application note of test mode, Table 3, there is description about what data is loaded in I/Q channel for a specific short pattern.
Customer would like to know if they want to do a PRBS31, is there any guide about the specific channel data need to match for checker?
Analog FAE from Shenzhen, China
The PRBS31 is a physical layer testing. Each lane (from the FPGA) will send out individual PRBS31 pattern, and each lane on the DAC will interpret it and check if the PRBS31 is received correctly. You do not need to separate it out on the JESD link layer level.
When testing PRBS31, please disable JESD_COMMAALIGN_ENA (set to 0) to ensure correctness of the PRBS31 testing.
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In reply to Kang Hsia:
Thank you very much!
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