I am looking at a base station design where I am interested in the possibility of using the GC6016 DDC/DUC and a C6670’ DSP. I would like to connect the GC6016 baseband output port directly to the DSP if at all possible. Have you heard of anyone doing this using the SRIO, HyperLink, DDR, or other interface? My other option of course is to use an FPGA in between but I would really like to not do this.
Please let me know your thoughts.
The interface is not SRIO or a standard Serdes interface. The GC533x and GC6016 family of DDC/DUC/CFR/DPD has a set of 12 LVDS signals for Receive, and 12 LVDS signals.
There is an FPGA reference design being developed for a Small-Cell-Initiative that converts the Serdes to the GC533x Baseband interface. If you have a DSP Field Application Engineer, they can send you more information on the Small-Cell-Initiative reference boards.
Has the FPGA reference design for the GC533x and GC6016 Small-Cell-Initiative that converts the Serdes to the GC533x Baseband interface been created?
I asked this question long enough ago that it's worth checking again, please let me know.
The GC5330, GC6016 EVM boards have an FPGA memory to LVDS Baseband Tx input interface. There is an LVDS to FPGA memory interface for the LVDS Baseband Rx output interface. The EVM interface projects are provided for specific business cases, and with license agreements.
Several customers have used an LVDS to FIFO, and FIFO to memory interface for their FPGA projects. The memory interface is then converted with an embedded processor to split or package the baseband IQ data and control messages.
The Small Cell Initiative DSP engineer is Eric Billingsley email@example.com . You can contact him related to the Small Cell Initiative FPGA solution for Serdes to GC533x / GC6016 LVDS interface.
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