In the tsw4100 eval board there is an altera fpga that among other enables ddc/duc programable sync.
Taking out 5016 and altera registers configutration interface, The questions are:
1. is this sync design a must, or connecting ddc sync out to duc sync in and internal sync configuration will work ?
2. why port ddc port c and d are routed through altera ? with 2+ clock delay ?
3. is there a special reason why ddc port ab are connected to duc port cd and ddc port cd are connected to duc port ab ?
Thanks
Jacob
Hello,
The GC5016 has a 2 channel and a 4 channel mode.
The 2 channel mode is called splitIQ, and used 2 DDC/DUC blocks per channel for more PFIR filtering.
The IO interface in this mode is either real I and realQ from DDC to DUC, or TDM interleaved QB,IB,QA,IA(the TDM is not supported in the current FPGA)
The 4 channel mode has different IO interface.
Interleaved I then Q, or TDM interleaved QD,ID,QC,IC,QB,IB,QA,IA (the TDM is not supported in the current FPGA)
1) If the customer follows the recommended IO interface for the GC5016 from the IO Application Note, the special Sync design is not needed.
2) in the splitIQ mode, we would register the parallel I and Q output from the DDC to a register. We would then transfer that register to the FPGA output register for the DUC.
2 sets of registers.
3) The TDM mode DDC is from portD, the TDM mode to the DUC is for portA. CD(DDC) is connected to AB(DUC) to allow for future expansion using TDM
Regards,
Radio Joe