I am in the process of designing an SDR transceiver card for a military application.
I would like to use the GC6016 with an ADC sample rate of roughly 125MSPS and produce baseband RX samples at 96KSPS rate. For TX operation I would like to feed 96KSPS baseband and feed the DAC at roughly 125 MSPS. In each case I would need to run 16 channels (or more if possible).
Is this within the capability of this chip? I am having an extremely difficult time getting information on this. Please advise. Thanks
As described in the GC6016 datasheet, table 22 note 1, there is a minimum PLL output requirement of 400MHz. This limitation prevents the chip to support a baseband interface sample rate of 96KSPS. The minimum baseband interface rate that can be supported is 2.4576MSPS. For your application, it will require an additional interpolator/decimator to resample the 96KSPS data to 2.4576MSPS.
Thanks for the quick response. I believe we will be talking on a conference call tomorrow, but I have some confusion about this requirement based on a previous related post (see below). The datasheet does not have any discusion of the PLL or how it relates to the DPD clock and BB clock. Can you elaborate?
Also, the part appears to have the ability to decimate by a maximum factor of 98,304 ( BDC x16, CIC x 3, FARROW x 1024, FIR x 2) so what is the purpose of this if the minimum BB rate is or the order of 2 MSPS?
Thanks for your help.
I cannot describe specific design details about gc6016 on public forum. Let's discuss about it on the conference call tomorrow.
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