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GC4016: question about CIC_SCALE

Hello all,

I'm trying to understand calculations of the DDC's overall gain and I have a trouble now with a formula for CIC_SCALE (bottom of page 18 of manual http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=gc4016&fileType=pdf&track=no):


Corresponding to chart the CIC_SCALE is a block for shift input signal just before CIC-filter.
With the biggest values (SHIFT=7, SCALE=5, BIG_SCALE=7)

CIC_SCALE = 2^(7+5+6*7-62)= 2^(-8)

Is this means that from input signal (20 bits) only 12 bits is passed to the CIC?
I can't believe that we shift the signal so strongly even for the best case.
Why we have to calculate NCO and mixer with 20-bits precision if we shift it immediately to 12 bits?

Please, help me to understand this.

  • Hello,

    There is an IEEE paper written by Hogenaur that explains the design components of the CIC.  The CIC integrator stages must not overflow.  The data is attenuated before being input to the 5 stage integrator.  On page 18 of the datasheet, the CIC integrator has a gain of N (CIC decimation)^5. 

    The GC4016 decimation structure is CIC -> CFIR Dec2 -> PFIR Dec2, then the resampler Int/Dec

    The Shift, Scale, and Big Scale are set as part of using the cmd4016 program that can be downloaded from the product page with examples.  In 4 channel mode, the CIC decimation starts at 8 and increases. 

    A 4016 gain spreadsheet is attached.


    Radio Joe


  • In reply to Radio-Joe:


    I have the same question regarding the huge don-scaling at the input to the CIC filter. I'm aware of the bit growth inside the filter. But I do not understand the logic of bits truncation (down-scaling) at the input to the filter. How are the input bits shifted and how are they packed inside the filter after the down-scaling? Do we loose bits due to the down-scaling? How many bits are generated after the down-scaling? We need some more info about the internal design of the CIC_SCALE circuit.