gc5316 power up

Is there any requirements to power up sequence of the chip?

First 3.3V, then 1.5V, or doesn't matter?

  • Hello Victor,

     

    The GC5316 has a 1.5v core, and 3.3vIO power .  The RESET_N signal should be held low on startup until the

    1.5v core and 3.3v IO are within tolerance.  As long as the RESET_N is low, the power supply sequece is not required.

    Both power supplies should be applied within 100ms.  Some hardware design to avoid MPU 3.3v bus contention, such as a pull up resistor

    for Chip_enable_N should also be used.

    Regards,

    Radio Joe

  • In reply to Radio-Joe:

    Just to be sure: Is RESET_N a full hardware reset?

    I mean this case:

    If RESET_N not tied low _while_ on startup, will i get the same result if i assert RESET_N low some time _after_ startup?

    I want to use FPGA to interface GC, but i think FPGA will not be already loaded while GC IO and core voltages are starting up...

    Or i should use some pulldown on RESET_N line?

     

    Thank you!

  • In reply to Victor:

    Hello Victor,

    A pull down resistor for the TRST and RESETN should be applied if the FPGA is not available to pull this low during startup.  The FPGA can output a '1' to these

    signals after the power supplies are OK.    The part is only tested with RESETN TRST low to high when the power supplies are off and then valid.

    Regards,

    Radio Joe