Hi I am trying to configure DDC GC5016 for LTE (data input rate 122.88 Msps to output 15.36 Msps (decimation of 8)).
Project details : We are initializing standalone GC5016 chip so sync_mode = 9, soB_sync =4, fir_sync =4, sck_sync =4, nco_sync=4,cic_sync=4.
The input is real full rate , 2 channel (port A and C) are being used. Output is 2-channel TDM splitIQ at D port.
sck_div=0, PFIR filter coefficients are 191 taps generated by Matlab code provided.
Issue : The input is 10 Mhz LTE data (8 times interpolated in Matlab) but the output is not coming perfect on the GC5016 evaluation board. The out of band attenuation is just 20 dB instead of desired 60-80 dB.
We have checked the filter in Matlab it works fine on the same input data without using DDC but with DDC the above issue is seen.
Is it the AGC gain setting or filter design or some other configuration parameter that is causing this issue ?
The decimate by 8 mode, sck_div =0 should result in the Frame Strobe being output one out of 8 clock cycles.
The data order should be BQ, BI, AQ, and AI.
You can substitute the internal diagnostic constant and set the two mixer frequencies for A and C to an inband output value (like .3Mhz and .5Mhz)
This will check that the GC5016 DDC, GC101, and GC Studio software can generate the proper output complex data.
On the TI EVM, the DDC input port A and B are available. Port C and D are connected to GND.
The agc is not functional in the splitIQ mode, set the overall_gain to 1.0. set the agc_freeze to 1, set the gain_sync to 7.
There are two filtering methods, ci cdec2, pfir dec 4, and cic dec4, pfir dec 2. PFIR dec of 2, has more filter taps, PFIR dec of 4 has better close-in stop band rejection control.
The DIP switches on the GC5016 DIMM need to be set for the proper output AB or CD ports. the first four switches are set to 0010 for AB and 1101 for CD (DDC TDM)
I have inlcuded zip file that has the input, project file, and pictures of the output for both 127 taps and 191 taps.
Thanks for your support. I figured out the problem. Actually the mixer was set to -44 while the input was baseband data interpolated by 8.
When I upconverted the baseband data to 44Mhz , output was fine.
I have another question regarding the NCO. The input sampling rate is 122.88 Msps and the NCO is generating 44 MHz . The two are not multiple of each othe.
Does that mean spectrum would corrupt or that I should use the phase offset(phase initialization) to get proper spectrum.
The GC5016 nco_sync will initialize the NCO phase to the phase offset value. The phase offset can be programmed once, and as such doesn't affect the
spectrum after initialization. If the SIA, SIB, or internal counter are used for repetitive syncing, then the NCO_sync set to these values, will cause a phase glitch
each time the NCO is synced. NCO_sync is usually only needed as a one time event,
If you don't need absolute phase control, set the nco_sync to 0.
I tried to run the DDC configuration on our own LTE IF board. I gave LTE input from VSG to the ADC --> FPGA-->DDC-->FPGA(stored in SRAM).
The power spectrum is coming to be proper but the constellation is too bad.What could be the reason for this.
Is it some sort of timing error on the different interfaces in the chain or is it some error related to DDC configuration or may be the gain setting ?
Could you help debug the same.
There are several DDC items that need to be reviewed in demodulating after the DDC.
a) what is the Frequency error as indicated on the Demodulator, you then need to retune the NCO to reduce the frequency error to the allowed range
b) if the signal demodulates, but is a higher EVM, the spectrum is not inverted. If there is no demodulation, the Nyquist zone and tuning selection may require
up converting the signal image, instead of down converting the standard signal, even number Nyquist zones need up conversion tuning from the ADC
c) looking at the signal amplitude of I and Q, check to make sure that there is some headroom .5 to 1db less than full scale or adjust the gain
d) check the GC5016 clock quality, using the output clock to the FPGA make sure the clock and Frame are the desired signalling rates
e) the PFIR taps can have a larger passband, if the peak EVM is related to the outer tone region of the OFDM waveform
I was able to debug the issue.I was not collecting enough i.e 1 frame (15360*2*10) samples in SRAM so this resulted in proper power spectrum but he decoding of LTE signal at VSA was not happening.
I have few more questions
1) In the configuration project you provided the sync signals are set to 2, which I believe is a requirement for multiple GC5016. In our case we are using standalone DDC, shouldn't I change the sync signals to 4.
2) The mix_rcv_sel selects one of the four input busses, in our case input is real, full rate data being applied to port A and C.In the GCStudio project we set mix_rcv_sel as patha. I didnt understand how the input on C port will be selected and processed by DDC.
The GC5016 can have several different sync configurations. Using a sync mode of 9, and sync_selects of 4 is fine for one device. On the TI EVM, we typically place in the Transmit memory a sync, we then set the SIA sync selects for sck_sync, fir_sync, and cic_sync. There is a 2nd sync offset in the Parameter menu that needs to be adjusted to place the interleaved IQ or Time Division multiplexed IQ at the proper time for the Frame Strobe signal for a DUC
The simplified answer to question 1 is that you can use sync_mode = 9, and sync_selects = 4.
Question 2) the GC5016 SEK only has digital inputs for ports A and B. If you would like to use Port C, you need to change this, once your base DDC design is OK.
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