It is planned to form clk by means of clock distribution chips (AD9510 or CDCM7005). How it is better to connect AD9510 and AFE8406?1. AFE8406 clkp - CMOS CLK AFE8406 clkm - ac-coupled with a capacitor2. AFE8406 clkp - CMOS CLK
AFE8406 clkm - inverted CMOS CLK3. LVPECL.
The AFE8406 has an internal dual ADC. There are upto 2 additional ADCs that can be connected to ports C and D. The ADC interfacing app notes,
Normally a differential sine source LvPECL is the lowest noise source. Please refer to http://focus.ti.com/lit/an/scaa092/scaa092.pdf
clkpa, clkma, clkpb, clkmb are a differential clock input, transformer coupled from a filtered sine source, or capacitor coupled LvPECL.
adcclkc, adcclkd are the output data clock from an ADC to the GC5018 / AFE8406.
You write:- clkpa, clkma, clkpb, clkmb are a differential clock input, transformer coupled from a filtered sine source, or capacitor coupled LvPECL.Normally, differential voltage levels for a LVPECL specifications: Vpp = 800 - 1000 mV.However, in datasheet AFE8406 p.4 "3.3 RECOMMENDED OPERATING CONDITIONS":Analog Chip Differential clock inputs Vpp nom. = 3V.
How it to understand?
Whether submission differential LVPECL is possible or isn't desirable? OR it is better to use single-ended 3.3V CMOS clock?
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