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Question about 'cic_div' for GC5016 DUC Input Timing

Hi Joe,

 In the datasheet P34-35, there are:1) The incoming data is clocked by the rising edge of the GC5016 clock CK;   2) The sck_div can be used to programe the GC5016 receive data every second,third,ect.,clock edge.

My question is that : Should sck_div  be set appropriatly that the number of sampling points in one Frame Strobe(FS) fit the input format.

>>>>>>>Assure that the input format is Interleaved IQ,16 bit, 16 pin. Under this configuration, it needs only 1 I data and 1 Q data in each FS period. It means that GC5016 samples twice in one FS period. Now,  if cic_int*fir_int = 16, there are 16 CK periods in one FS period. According to 1) and 2) , if sck_div is set to 1,  GC5016 will sample 8 times in one FS period. Is there any problems because Interleaved IQ input needs only two sampling points ?