Hi community of Texas Instrumen, Thans for your time
Please I need help with cc1120 + msp430F5528. I am development my drivers for the interface SPI between the msp430F5528 and the cc1120. The problem is that I get error in the Tx FIFO when I attempt send a data. This is my code:
#include <msp430f5528.h>
#define Port_with_CS_CC11xx (P3OUT)
#define CS_CC11xx (BIT3)
#define ByteTx_spi_CC11xx (UCB0TXBUF)
#define ByteRx_spi_CC11xx (UCB0RXBUF)
#define Flag_Interrupt_TxSPI_Memory (BIT1) //ok
#define Flag_Interrupt_RxSPI_Memory (BIT0) //ok
#define Register_Interrupt_SPI_Memory (UCB1IFG)//ok
#define Flag_Interrupt_TxSPI_CC11xx (BIT1)//ok
#define Flag_Interrupt_RxSPI_CC11xx (BIT0)//ok
#define Register_Interrupt_SPI_CC11xx (UCB0IFG)//ok
#define TI_CC_GDO3_PxSEL P2SEL
#define TI_CC_GDO3_PxOUT P2OUT
#define TI_CC_GDO3_PxIN P2IN
#define TI_CC_GDO3_PxDIR P2DIR
#define TI_CC_GDO3_PxIE P2IE
#define TI_CC_GDO3_PxIES P2IES
#define TI_CC_GDO3_PxIFG P2IFG
#define TI_CC_GDO3_PIN BIT6
#define TI_CC_GDO1_PxSEL P2SEL
#define TI_CC_GDO1_PxIN P2IN
#define TI_CC_GDO1_PxDIR P2DIR
#define TI_CC_GDO1_PIN BIT5
// Configuration Registers
#define ADD_CCxxx0_IOCFG3 0x00 // GDO3 output pin configuration
#define ADD_CCxxx0_IOCFG2 0x01 // GDO2 output pin configuration
#define ADD_CCxxx0_IOCFG1 0x02 // GDO1 output pin configuration
#define ADD_CCxxx0_IOCFG0 0x03 // GDO0 output pin configuration
#define ADD_CCxxx0_SYNC3 0x04
#define ADD_CCxxx0_SYNC2 0x05
#define ADD_CCxxx0_SYNC1 0x06
#define ADD_CCxxx0_SYNC0 0x07
#define ADD_CCxxx0_SYNC_CFG1 0x08
#define ADD_CCxxx0_SYNC_CFG0 0x09
#define ADD_CCxxx0_DEVIATION_M 0x0A
#define ADD_CCxxx0_MODCFG_DEV_E 0x0B
#define ADD_CCxxx0_DCFILT_CFG 0x0C
#define ADD_CCxxx0_PREAMBLE_CFG1 0x0D
#define ADD_CCxxx0_PREAMBLE_CFG0 0x0E
#define ADD_CCxxx0_FREQ_IF_CFG 0x0F
#define ADD_CCxxx0_IQIC 0x10
#define ADD_CCxxx0_CHAN_BW 0x11
#define ADD_CCxxx0_MDMCFG1 0x12
#define ADD_CCxxx0_MDMCFG0 0x13
#define ADD_CCxxx0_SYMBOL_RATE2 0x14
#define ADD_CCxxx0_SYMBOL_RATE1 0x15
#define ADD_CCxxx0_SYMBOL_RATE0 0x16
#define ADD_CCxxx0_AGC_REF 0x17
#define ADD_CCxxx0_AGC_CS_THR 0x18
#define ADD_CCxxx0_AGC_GAIN_ADJUST 0x19
#define ADD_CCxxx0_AGC_CFG3 0x1A
#define ADD_CCxxx0_AGC_CFG2 0x1B
#define ADD_CCxxx0_AGC_CFG1 0x1C
#define ADD_CCxxx0_AGC_CFG0 0x1D
#define ADD_CCxxx0_FIFO_CFG 0x1E
#define ADD_CCxxx0_DEV_ADDR 0x1F
#define ADD_CCxxx0_SETTLING_CFG 0x20
#define ADD_CCxxx0_FS_CFG 0x21
#define ADD_CCxxx0_WOR_CFG1 0x22
#define ADD_CCxxx0_WOR_CFG0 0x23
#define ADD_CCxxx0_WOR_EVENT0_MSB 0x24
#define ADD_CCxxx0_WOR_EVENT0_LSB 0x25
#define ADD_CCxxx0_PKT_CFG2 0x26
#define ADD_CCxxx0_PKT_CFG1 0x27
#define ADD_CCxxx0_PKT_CFG0 0x28
#define ADD_CCxxx0_RFEND_CFG1 0x29
#define ADD_CCxxx0_RFEND_CFG0 0x2A
#define ADD_CCxxx0_PA_CFG2 0x2B
#define ADD_CCxxx0_PA_CFG1 0x2C
#define ADD_CCxxx0_PA_CFG0 0x2D
#define ADD_CCxxx0_PKT_LEN 0x2E
// Strobe commands
#define ADD_CCxxx0_SRES 0x30 // Reset chip.
#define ADD_CCxxx0_SFSTXON 0x31 // Enable/calibrate freq synthesizer
#define ADD_CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
#define ADD_CCxxx0_SCAL 0x33 // Calibrate freq synthesizer & disable
#define ADD_CCxxx0_SRX 0x34 // Enable RX.
#define ADD_CCxxx0_STX 0x35 // Enable TX.
#define ADD_CCxxx0_SIDLE 0x36 // Exit RX / TX
#define ADD_CCxxx0_SAFC 0x37 // AFC adjustment of freq synthesizer
#define ADD_CCxxx0_SWOR 0x38 // Start automatic RX polling sequence
#define ADD_CCxxx0_SPWD 0x39 // Enter pwr down mode when CSn goes hi
#define ADD_CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
#define ADD_CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
#define ADD_CCxxx0_SWORRST 0x3C // Reset real time clock.
#define ADD_CCxxx0_SNOP 0x3D // No operation.
// Status registers
#define ADD_CCxxx0_PARTNUM 0x30 // Part number
#define ADD_CCxxx0_VERSION 0x31 // Current version number
#define ADD_CCxxx0_FREQEST 0x32 // Frequency offset estimate
#define ADD_CCxxx0_LQI 0x33 // Demodulator estimate for link quality
#define ADD_CCxxx0_RSSI 0x34 // Received signal strength indication
#define ADD_CCxxx0_MARCSTATE 0x35 // Control state machine state
#define ADD_CCxxx0_WORTIME1 0x36 // High byte of WOR timer
#define ADD_CCxxx0_WORTIME0 0x37 // Low byte of WOR timer
#define ADD_CCxxx0_PKTSTATUS 0x38 // Current GDOx status and packet status
#define ADD_CCxxx0_VCO_VC_DAC 0x39 // Current setting from PLL cal module
#define ADD_CCxxx0_TXBYTES 0x3A // Underflow and # of bytes in TXFIFO
#define ADD_CCxxx0_RXBYTES 0x3B // Overflow and # of bytes in RXFIFO
#define ADD_CCxxx0_NUM_RXBYTES 0x7F // Mask "# of bytes" field in _RXBYTES
// Other memory locations
#define ADD_CCxxx0_PATABLE 0x3E
#define ADD_CCxxx0_TXFIFO 0x3F
#define ADD_CCxxx0_RXFIFO 0x3F
// Masks for appended status bytes
#define ADD_CCxxx0_LQI_RX 0x01 // Position of LQI byte
#define ADD_CCxxx0_CRC_OK 0x80 // Mask "CRC_OK" bit within LQI byte
// Definitions to support burst/single access:
#define ADD_CCxxx0_WRITE_BURST 0x40
#define ADD_CCxxx0_READ_SINGLE 0x80
#define ADD_CCxxx0_READ_BURST 0xC0
// Configuration Registers
char VAL_CCxxx0_IOCFG3 = 0x06; // GDO3 output pin configuration
char VAL_CCxxx0_IOCFG2 = 0x07; // GDO2 output pin configuration
char VAL_CCxxx0_IOCFG1 = 0x30; // GDO1 output pin configuration
char VAL_CCxxx0_IOCFG0 = 0x3C; // GDO0 output pin configuration
char VAL_CCxxx0_SYNC3 = 0x93;
char VAL_CCxxx0_SYNC2 = 0x0B;
char VAL_CCxxx0_SYNC1 = 0x51;
char VAL_CCxxx0_SYNC0 = 0xDE;
char VAL_CCxxx0_SYNC_CFG1 = 0x0A;
char VAL_CCxxx0_SYNC_CFG0 = 0x17;
char VAL_CCxxx0_DEVIATION_M = 0x06;
char VAL_CCxxx0_MODCFG_DEV_E = 0x03;
char VAL_CCxxx0_DCFILT_CFG = 0x4C;
char VAL_CCxxx0_PREAMBLE_CFG1 = 0x14;
char VAL_CCxxx0_PREAMBLE_CFG0 = 0x2A;
char VAL_CCxxx0_FREQ_IF_CFG = 0x40;
char VAL_CCxxx0_IQIC = 0xC4;
char VAL_CCxxx0_CHAN_BW = 0x14;
char VAL_CCxxx0_MDMCFG1 = 0x46;
char VAL_CCxxx0_MDMCFG0 = 0x0D;
char VAL_CCxxx0_SYMBOL_RATE2 = 0x43;
char VAL_CCxxx0_SYMBOL_RATE1 = 0xA9;
char VAL_CCxxx0_SYMBOL_RATE0 = 0x2A;
char VAL_CCxxx0_AGC_REF = 0x36;
char VAL_CCxxx0_AGC_CS_THR = 0x00;
char VAL_CCxxx0_AGC_GAIN_ADJUST = 0x00;
char VAL_CCxxx0_AGC_CFG3 = 0x91;
char VAL_CCxxx0_AGC_CFG2 = 0x20;
char VAL_CCxxx0_AGC_CFG1 = 0xAA;
char VAL_CCxxx0_AGC_CFG0 = 0xC3;
char VAL_CCxxx0_FIFO_CFG = 0x80;
char VAL_CCxxx0_DEV_ADDR = 0x00;
char VAL_CCxxx0_SETTLING_CFG = 0x0B;
char VAL_CCxxx0_FS_CFG = 0x02;
char VAL_CCxxx0_WOR_CFG1 = 0x08;
char VAL_CCxxx0_WOR_CFG0 = 0x21;
char VAL_CCxxx0_WOR_EVENT0_MSB = 0x00;
char VAL_CCxxx0_WOR_EVENT0_LSB = 0x00;
char VAL_CCxxx0_PKT_CFG2 = 0x04;
char VAL_CCxxx0_PKT_CFG1 = 0x05;
char VAL_CCxxx0_PKT_CFG0 = 0x00;
char VAL_CCxxx0_RFEND_CFG1 = 0x0F;
char VAL_CCxxx0_RFEND_CFG0 = 0x00;
char VAL_CCxxx0_PA_CFG2 = 0x7F;
char VAL_CCxxx0_PA_CFG1 = 0x56;
char VAL_CCxxx0_PA_CFG0 = 0x7C;
char VAL_CCxxx0_PKT_LEN = 0x03;
char Temp;
void config_reloj (void);
void config_port(void);
void config_SPI_CC11xx(void);
void TI_CC_PowerupResetCCxxxx(void);
void TI_CC_SPIStrobe(char);
void TI_CC_SPIWriteReg(char,char);
void Write_Byte_RF(char);
char Read_Byte_RF(void);
int main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;
Register_Interrupt_SPI_CC11xx &= ~Flag_Interrupt_TxSPI_CC11xx;
Register_Interrupt_SPI_CC11xx &= ~Flag_Interrupt_RxSPI_CC11xx;
Register_Interrupt_SPI_Memory &= ~Flag_Interrupt_TxSPI_Memory;
Register_Interrupt_SPI_Memory &= ~Flag_Interrupt_RxSPI_Memory;
REFCTL0 &= ~REFMSTR;
__delay_cycles(5000);
__bis_SR_register(GIE);
//config_reloj ();
config_port();
config_SPI_CC11xx();
TI_CC_PowerupResetCCxxxx();
TI_CC_SPIWriteReg(ADD_CCxxx0_IOCFG3, VAL_CCxxx0_IOCFG3 );
TI_CC_SPIWriteReg(ADD_CCxxx0_IOCFG2 ,VAL_CCxxx0_IOCFG2 );
TI_CC_SPIWriteReg(ADD_CCxxx0_IOCFG1 ,VAL_CCxxx0_IOCFG1 );
TI_CC_SPIWriteReg(ADD_CCxxx0_IOCFG0 ,VAL_CCxxx0_IOCFG0 );
TI_CC_SPIWriteReg(ADD_CCxxx0_SYNC3,VAL_CCxxx0_SYNC3);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYNC2,VAL_CCxxx0_SYNC2);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYNC1,VAL_CCxxx0_SYNC1);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYNC0,VAL_CCxxx0_SYNC0);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYNC_CFG1,VAL_CCxxx0_SYNC_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYNC_CFG0,VAL_CCxxx0_SYNC_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_DEVIATION_M,VAL_CCxxx0_DEVIATION_M);
TI_CC_SPIWriteReg(ADD_CCxxx0_MODCFG_DEV_E,VAL_CCxxx0_MODCFG_DEV_E);
TI_CC_SPIWriteReg(ADD_CCxxx0_DCFILT_CFG,VAL_CCxxx0_DCFILT_CFG);
TI_CC_SPIWriteReg(ADD_CCxxx0_PREAMBLE_CFG1,VAL_CCxxx0_PREAMBLE_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_PREAMBLE_CFG0, VAL_CCxxx0_PREAMBLE_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_FREQ_IF_CFG,VAL_CCxxx0_FREQ_IF_CFG);
TI_CC_SPIWriteReg(ADD_CCxxx0_IQIC,VAL_CCxxx0_IQIC);
TI_CC_SPIWriteReg(ADD_CCxxx0_CHAN_BW,VAL_CCxxx0_CHAN_BW);
TI_CC_SPIWriteReg(ADD_CCxxx0_MDMCFG1, VAL_CCxxx0_MDMCFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_MDMCFG0,VAL_CCxxx0_MDMCFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYMBOL_RATE2, VAL_CCxxx0_SYMBOL_RATE2);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYMBOL_RATE1, VAL_CCxxx0_SYMBOL_RATE1);
TI_CC_SPIWriteReg(ADD_CCxxx0_SYMBOL_RATE0, VAL_CCxxx0_SYMBOL_RATE0);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_REF, VAL_CCxxx0_AGC_REF);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_CS_THR,VAL_CCxxx0_AGC_CS_THR);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_GAIN_ADJUST,VAL_CCxxx0_AGC_GAIN_ADJUST);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_CFG3,VAL_CCxxx0_AGC_CFG3);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_CFG2,ADD_CCxxx0_AGC_CFG2);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_CFG1,ADD_CCxxx0_AGC_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_AGC_CFG0,ADD_CCxxx0_AGC_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_FIFO_CFG,VAL_CCxxx0_FIFO_CFG);
TI_CC_SPIWriteReg(ADD_CCxxx0_DEV_ADDR,VAL_CCxxx0_DEV_ADDR);
TI_CC_SPIWriteReg(ADD_CCxxx0_SETTLING_CFG,VAL_CCxxx0_SETTLING_CFG);
TI_CC_SPIWriteReg(ADD_CCxxx0_FS_CFG,VAL_CCxxx0_FS_CFG);
TI_CC_SPIWriteReg(ADD_CCxxx0_WOR_CFG1,VAL_CCxxx0_WOR_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_WOR_CFG0,VAL_CCxxx0_WOR_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_WOR_EVENT0_MSB,VAL_CCxxx0_WOR_EVENT0_MSB);
TI_CC_SPIWriteReg(ADD_CCxxx0_WOR_EVENT0_LSB,VAL_CCxxx0_WOR_EVENT0_LSB);
TI_CC_SPIWriteReg(ADD_CCxxx0_PKT_CFG2,VAL_CCxxx0_PKT_CFG2);
TI_CC_SPIWriteReg(ADD_CCxxx0_PKT_CFG1,VAL_CCxxx0_PKT_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_PKT_CFG0,VAL_CCxxx0_PKT_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_RFEND_CFG1,VAL_CCxxx0_RFEND_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_RFEND_CFG0,VAL_CCxxx0_RFEND_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_PA_CFG2,VAL_CCxxx0_PA_CFG2);
TI_CC_SPIWriteReg(ADD_CCxxx0_PA_CFG1,VAL_CCxxx0_PA_CFG1);
TI_CC_SPIWriteReg(ADD_CCxxx0_PA_CFG0,VAL_CCxxx0_PA_CFG0);
TI_CC_SPIWriteReg(ADD_CCxxx0_PKT_LEN,VAL_CCxxx0_PKT_LEN);
TI_CC_SPIStrobe(ADD_CCxxx0_SFRX);
TI_CC_SPIStrobe(ADD_CCxxx0_SFTX);
TI_CC_SPIStrobe(ADD_CCxxx0_SRX); // Initialize CCxxxx in RX mode.
// When a pkt is received, it will
// signal on GDO0 and wake CPU
Write_Byte_RF(0xA7);
__delay_cycles(5000);
// Temp = Read_Byte_RF();
while(1);
}
////////////////////// Function for configurate ////////////////////////////////
//////////////// Configurate the clk ///////////////////////////////////////
void config_reloj ()
{
UCSCTL6 = 0x0100;
__delay_cycles(500000);
Temp = UCSCTL7 & 0x0002;
while(Temp != 0)
{
UCSCTL7 &= ~XT1LFOFFG;
__delay_cycles(500000);
Temp = UCSCTL7 & 0x0002;
}
UCSCTL0 = 0x1300; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_2; // Select DCO range 24MHz operation
UCSCTL4 = 0x0004; // ACLK = XT1, MCLK = SMCLK = XT2
}
////////////////////////////////////////////////////////////////////////////////
///////////////////////// Configurate I2C //////////////////////////////////////
void config_SPI_CC11xx() // Cofigurate the I2C
{
UCB0CTL0 |= UCSWRST;//UCB1CTL1 |= UCSWRST;
UCB0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC;//UCB1CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC; // Sincrónoco y Master
UCB0CTL1 |= UCSSEL1;//UCB1CTL1 = UCSSEL1; // Reloj SMCLK
UCB0BR0 = 5;//UCB1BR0 = 5; // Baud rate //0x04
UCB0BR1 = 0; // Baud rate
P3SEL = 0x00;
P3SEL |= BIT0 + BIT1 + BIT2;
P3DIR = 0xFF;
P3DIR &= ~BIT1;
P3OUT = 0x00;
Port_with_CS_CC11xx |= CS_CC11xx;
UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCB0IE |= UCRXIE + UCTXIE; // Habilito interrupción USCIA1 Tx
}
////////////////////////////////////////////////////////////////////////////////
void config_port(void)
{
// Enable Interrupt for GDO3 when Rx Package
TI_CC_GDO3_PxSEL &= ~TI_CC_GDO3_PIN; // I/O
TI_CC_GDO3_PxDIR &= ~TI_CC_GDO3_PIN; // Input
TI_CC_GDO3_PxIES |= TI_CC_GDO3_PIN; // Int on falling edge (end of pkt)
TI_CC_GDO3_PxIFG &= ~TI_CC_GDO3_PIN; // Clear flag
TI_CC_GDO3_PxIE |= TI_CC_GDO3_PIN; // Enable int on end of packet
// Input for Testing SO
TI_CC_GDO1_PxSEL &= ~TI_CC_GDO1_PIN; // I/O
TI_CC_GDO1_PxDIR &= ~TI_CC_GDO1_PIN; // Input
}
//////////////////////////// Reset CC11xx /////////////////////////////////////
void TI_CC_PowerupResetCCxxxx(void)
{
Port_with_CS_CC11xx |= CS_CC11xx;
__delay_cycles(30);
Port_with_CS_CC11xx &= ~CS_CC11xx; // /CS enable
while ((TI_CC_GDO1_PxIN & TI_CC_GDO1_PIN ) != 0x00); // Wait for TXBUF ready
ByteTx_spi_CC11xx = ADD_CCxxx0_SRES; // Send strobe
// Strobe addr is now being TX'ed
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
Port_with_CS_CC11xx |= CS_CC11xx; // /CS disable
}
void TI_CC_SPIStrobe(char strobe)
{
Port_with_CS_CC11xx |= CS_CC11xx;
__delay_cycles(30);
Port_with_CS_CC11xx &= ~CS_CC11xx; // /CS enable
while ((TI_CC_GDO1_PxIN & TI_CC_GDO1_PIN ) != 0x00); // Wait for TXBUF ready
ByteTx_spi_CC11xx = strobe;
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
Port_with_CS_CC11xx |= CS_CC11xx; // /CS disable
}
void TI_CC_SPIWriteReg(char addr, char value)
{
Port_with_CS_CC11xx |= CS_CC11xx;
__delay_cycles(30);
Port_with_CS_CC11xx &= ~CS_CC11xx; // /CS enable
while ((TI_CC_GDO1_PxIN & TI_CC_GDO1_PIN ) != 0x00); // Wait for TXBUF ready
ByteTx_spi_CC11xx = 0x2F; // Send address
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
ByteTx_spi_CC11xx = addr; // Send address
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
ByteTx_spi_CC11xx = value; // Send data
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
Port_with_CS_CC11xx |= CS_CC11xx; // /CS disable
}
char Read_Byte_RF(void)
{
Port_with_CS_CC11xx |= CS_CC11xx;
__delay_cycles(30);
Port_with_CS_CC11xx &= ~CS_CC11xx; // /CS enable
while ((TI_CC_GDO1_PxIN & TI_CC_GDO1_PIN ) != 0x00); // Wait for TXBUF ready
ByteTx_spi_CC11xx = 0xBF; // Send address
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
ByteTx_spi_CC11xx = 0; // Send address
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
Port_with_CS_CC11xx |= CS_CC11xx;
return ByteRx_spi_CC11xx;
}
void Write_Byte_RF(char ByteTx)
{
// TI_CC_SPIStrobe(ADD_CCxxx0_STX);
Port_with_CS_CC11xx |= CS_CC11xx;
__delay_cycles(30);
Port_with_CS_CC11xx &= ~CS_CC11xx; // /CS enable
while ((TI_CC_GDO1_PxIN & TI_CC_GDO1_PIN ) != 0x00); // Wait for TXBUF ready
ByteTx_spi_CC11xx = 0x3F; // Send address // Send address
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
for (int j = 3; j > 0; j--)
{
ByteTx_spi_CC11xx = ByteTx; // Send address
}
while(Register_Interrupt_SPI_CC11xx & Flag_Interrupt_TxSPI_CC11xx);// Wait for TX complete
Port_with_CS_CC11xx |= CS_CC11xx;
TI_CC_SPIStrobe(ADD_CCxxx0_STX);
}
#pragma vector=USCI_B0_VECTOR
__interrupt void TXRXSPI_CC11xx(void)
{
Register_Interrupt_SPI_CC11xx &= ~Flag_Interrupt_TxSPI_CC11xx;
Register_Interrupt_SPI_CC11xx &= ~Flag_Interrupt_RxSPI_CC11xx;
}
// The ISR assumes the int came from the pin attached to GDO0 and therefore
// does not check the other seven inputs. Interprets this as a signal from
// CCxxxx indicating packet received.
#pragma vector=PORT2_VECTOR
__interrupt void port2_ISR (void)
{
TI_CC_GDO3_PxIFG = 0;
}