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Part Number: LM97593
Currently we use the LM97593 with an input 21.400 MHz analog signal. Clock input to the LMS97593 is 22.05 MHz, creating an internal IF of 650kHz. The NCO is programmed to down-convert to dc, and we use a decimation of 2*2*75 to generate a net 73.5kHz output sample rate to our DSP.
We want to increase the input analog signal to 90MHz. Since the LM97593 is limited to Fck=65MHz, we have to choose an input clock much less than the input signal. Say this is 52.038 MHz, resulting in an internal IF of 37.962MHz. Question 1 - is it possible to generate an internal NCO frequency of 37.962MHz to translate this to dc? Question 2 - is it as simple then to set the decimation then, to (2*2*177). which equals 708, so as to maintain the net 73.5kHz output sample rate that we currently have? This is our desire.
Sorry for the delay in responding.
I think what you want to do should all be possible.
For Fin = 90 MHz and Fs = 52.038 MHz, I think the IF will be at 14.076MHz. The NCO can be set very close to + or - 14.076MHz.
The decimation factor can be set to 708 total. (177 * 2 * 2 for the CIC and 2 stage post CIC filters respectively)
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