I'm trying to implement Application Note SCAA088 to generate a master clock from a I2S source (from a CD player). But I'm having some troubles getting it to work as the PLL is not locking (and thus the output is running freely and not in sink with the input source). This is my schematic:
I've set the output dividers properly to the desired values (Y1 outputs a clock of 44.1KHz, Y2 has half the crystal frequency) and the CDCE913 is configured to operate in VCXO mode. But it seems like the signal from the phase comparator is not arriving properly at the CDCE913. (it's flat zero). when removing the RC-filter, this is what I see on the oscilloscope:
Still no difference in the locking of the PLL however... Does anyone have some pointers for my to try?
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In reply to Lane Boyd:
With the configuration file you mean the register settings written to the CDCE913? (i'm writing to it using a microcontroller)
The crystal used is a ABL-11.2896MHz-B4Y. I've attached the datasheet.
Thanks for looking into this!
Niek ten Brinke
Here are the register settings that are written to the CDCE913:
Forgot to say, but we removed the capacitors from the board (and set the internal caps to 20pF as you can read above)
In reply to Niek ten Brinke:
In reply to Dean Banerjee:
Thanks for your time! Small comment: the 'op-amp' isn't an op-amp, it's a comparator with an open drain output ;) If I understand it correctly, it's clamping the voltage to 1V8...
Regarding to 2: that shut R has a value of 0, so I guessed I could leave it out as well?
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