Can any help in programming the IC TRF 1112 (Dual VCO/PLL Synthesizer With IF Downconversion) .
You may post questions related to the TRF1112 device and its programming in this forum; however, please note that the TRF1112 is not recommended for new designs.
I have few questions in programming trf 1112 IC.
we are using TRF1x12 software control window for programming the TRF
1112 IC. In that window one config button is there. if we click on that
another box "In par Port" will open. In that LPT1 ADDR,clk, DATA, LE
buttons are there. I want to know what values ( for LPT1 ADDR, CLK, DATA, LE) we have to set.
if we power off and on the trf 1112 device, then whether programmed data remains in the trf 1112 ic or we need to program agian?
The default Parallel Port selections are set up for interfacing with the TRF1112 EVM. The numeric values for the Clk, Data, LE correspond to the output pin on which those signals will be sent on the parallel port. These values can be set to anything desired as long as they are connected to the Clk, Data, and LE pins of the IC appropriately. The LPT1 Address specifies which parallel port is being accessed. Generally there is only one so this value should remain unchanged.
The TRF1112 will loose its programming when powered off so it will need to be reprogrammed once powered on again.
The TRF1112 will loose its programming when powered off. so, I want program it using the microcontroller.
I have few questions in the regard.
In the data sheet of TRF 1112, the serial Interface of Timing Diagram(figure 9 Dual VCO/PLL Synthesizer With IF Downconversion (Rev. A)),
when EN=0, and CLK=1; the Data loaded serially into the TRF1112. after
loading the 24 bits(3 bytes ) of data, EN becomes 1 and after EPWH duration EN
becomes 0, then next 24bits (3 bytes) of data is loaded into TRF 1112.
this process continues for 9 bytes of data.
This is my understanding. is it correct?
What could be the appropriate frequency for the CLK signal?
What are could be typical values for the EPWH , ELC, CPWH, CPWL,CEL,DvC and CDl?
what could be the maximum values of N and S (LO1 and LO2) for TRF 1112 IC ?
Thanks and Regards
Your understanding of Figure 9 is correct. The clock signal can support a maximum clock rate of 20 MHz, but it can be slower. The minimum values for the timing requirements are listed in the datasheet on page 6.
The N-counter is a 6-bit word corresponding to a maximum value of 63. The S-counter is a 3-bit word corresponding to a maximum value of 7. However, you will not be able to use all combinations of the N and S counter becuase of limitations in the VCO. Reference the Synthesizer #1 and #2 tables that show the min and max values of the synthesizers. These min and max values will ultimately set the usuable values of the N and S counters.
What is charge pump current (Icp) or Kphi design value which is used to design the loop filter in TRF 1112?. Give us the design procedure for loop filter and specifications of PLL such as loop bandwidth , lock time and Kphi.
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