LMX2541 Evaluation board won't lock

I'm using an LMX25412380 EBI board to generate a 2.41176 GHz ADC sampling clock based on the 500 MHz reference in our synchrotron light source storage ring.  I've modified the board to accept an external clock signal rather than using the on-board 100 MHz oscillator.  The LOCK indicator LED never lights and the output is stuck at 2.436 GHz (+5 dBm) even when the 500 MHz (0 dBm) reference is moved up and down a MHz or so.

Here's how I've configured the LMX2541.  The design tool seems happy with these numbers.

Suggestions welcomed.

/*
 * Configure PLL
 * Fout = Fin * (PLL_N + PLL_NUM/PLL_DEN) / PLL_R / VCO_DIV = Fin * NUM / DEN
 *
 * Choose PLL_R=5 (Fpd = 500 MHz / 5 = 100 MHz)
 *  * Use NUM=82, DEN=17 (Fout=2.41176 GHz, Fsamp=1.20588 GHz, Tsamp=829.26829 ps)
 * 13448 samples per revolution (41 samples per bucket * 328 buckets)
 * Equivalent Fsamp=20.5 GHz
 *
 * Yields PLL_N=24  PLL_NUM=2  PLL_DEN=17  PLL_R=5  VCO_DIV=1
 */
void
pllConfig(void)
{
      /* R7 -- Reset PL */
      pllConfigWrite(0x00000017);
      /* R13 -- VCO_DIV_OPT=0 (Since RFout Pin disabled) */
    pllConfigWrite(0x0000008D);
    /* R12, R9  -- As described in data sheet */
    pllConfigWrite(0x0000001C);
    pllConfigWrite(0x28001409);
    /* R8 -- AC_TEMP_COMP=24 -- optimum for fixed-frequency application */
    pllConfigWrite(0x0111CF88);
     /*R6 -- DIVGAIN, VCOGAIN, OUTTERM=12 (default), RFOUT=2 (Enabled) */
    pllConfigWrite(0x001F3326);
    /* R5 -- All values=0 (no fast lock) */
    pllConfigWrite(0xA0000005);
    /* R4 -- C4_LF=4 (40 pF), C3_LF=4 (10 pF), R4_LF=0 (200 ohms),
     *       R3_LF=0 (200 ohms), VCO_DIV=1, OSC_FREQ=255 (since Fin > 255 MHz)
     * With these values and the existing 2.2nF C1, 470 ohm R2 and 22 nF C2
     * on the board the design tool reports a phase margin of 39.3 degrees
     * and jitter at the RF output of 148 fs RMS.*/
    pllConfigWrite(0x44001FF4);
    /* R3 -- FSK=0, DLOCK=0, CPT=0, DITH=3 (disabled), ORDER=3, FDM=1,
     *       OSC2x=0, CPP=0, MUX=3 (Digital lock detect),
     *       CPG=31 (3.2 mA, gives lower jitter), XO=0,
     *       POWERDOWN=0, MODE=0
     */
     pllConfigWrite(0x01B87F03);
    /*  R2 -- PLL_DEN=17 */
    pllConfigWrite(0x04000112);
    /* R1 -- PLL_NUM=2:[21:16]=0, PLL_N:24[17:12]=0, PLL_R=5 */
    pllConfigWrite(0x00000051);
    /* R0 -- PLL_NUM=2, PLL_N=24 */   
     pllConfigWrite(0x00020180);
}