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High Performance RF Modulators, PLL and VCO products
High Performance RF Modulators, PLL and VCO products Forum
LMX2541SQ2060E: How do keep the VCO in lock?
In datasheet it’s stated on chapter 3.7 page 54 that it should be possible to on/off the RFout pin while VCO still running and in lock.
They are looking at the RFout on a spectrum analyzator and when at the same time looking at the lock detect signal they can see it will unlock when toggle the on/off control.
Is there any frequency pulling who makes it unlock and why does it do it with the 50ohm?
They use VCO_DIV>1 and VCOGAIN=3, OUTTERM=2 and DIVGAIN=2.
They have tried VCOGAIN=12, OUTTERM=3 and DIVGAIN=12 who should give close to 50 ohm output impedance mentioned in table on page 23 in the datasheet.
But it didn’t help.
Are there any fix or setting to keep the VCO locked or do you have any recommended external fix?
I had to go back into the lab to verify this and I see what you are talking about.
When the output is enabled or disabled, then indeed there will be some disturbance of some magnitude. However, how much of a disturbance is considered out of lock is subjective. The digital lock detect is fairly sensitive, so when I had this set to a setting of 3 ns, then indeed I saw the lock detect pin momentarily go low, but then it would recover back to high. However, when I increased this setting for the DLOCK bit to a larger value, then this went away.
The lock detect settings depend on the phase detector frequency and modulator order, so I don't know what your exact situation is, but regardless, the fix is to increase the setting of the DLOCK bit to a bigger value to make the lock detect circuit less sensitive.
The statement in the datasheet is really intending to say that the PLL does not have to fully relock over the whole range and the VCO does not need to do redo another calibration routine. The frequency pulling spec in the datasheet is +/- 60 kHz for a 6 dB pad. A 60 kHz disturbance would probably be enough to trip the lock detect circuit in the more sensitive settings that we have for it.
Right, the customer reverted back to the evm for test but is still getting the same problem, settings attached.
I see the settings, but DLOCK is set to 3 ns, which is where I replicated the problem.
Change the value of DLOCK to 15.5 ns.
Also, I see you have 25 kHz phase detector frequency, which is fairly low and probably implies a narrow loop bandwidth. This in turn implies it is harder for the PLL to recover from the glitch of turning the buffer on and off. Consider raising the phase detector frequency and using fractional mode and perhaps a little bit wider loop bandwidth.
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