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LMX2492 PLL figure of Merit / normalized phase noise floor in frac-N mode

Novak Farrington
Prodigy 20 points
Other Parts Discussed in Thread: LMX2492

Hi All,

The data sheet for the LMX2492 quotes a PLL figure of merit (otherwise known as the normalized phase noise floor) of -227dBc/Hz.

1) Could anyone confirm this is for Integer N operation? (This does not seem to be specified or inferred in any way on the data sheet (Analog Devices will typically quote two figures, both integer and fractional values on their PLL chip data sheets))

2) If this is the integer value, does anyone have any information on the factional N value?

Thanks in advance and kind regards,

Novak

  • 0
    TI__Mastermind 27581 points

    Novak,

    We have found that the most accurate representaions of PLL integer phase noise are done when it is decomponsed into 2 independent elements.

    1.  PLL Flat Noise -- This is determined by figure of merit  (-227 for this part)

    2.  PLL 1/f Noise  -  This is determined by the PLL noirmalized 1/f noise (-120 for this device).

    The typical performance plot on page 8 shows the measurement for the PLL flat and 1/f noise in integer mode.  On the typical performance plots, page 8, it shows the basis for this measurement of the PLL Figure of merit.   Note that the PLL noise is the summation of the theoretical flat noise and theoretical 1/f noise.

    For fractional mode, it depends on the fraction.  For instance, if dithering is disabled, typically the noise floor does not degrade at all and just spurs are added.  I you use strong dithering and big fractions, then the figure of merit is as folows:   1st order Modulator:  -227, 2nd Order modulator: -223, 3rd Order Modulator: -219, 4th Order Modulator:  -210.

    The LMX2492 gives a lot of flexibility for adjusting dithering, modulator order, and fraction to get the best trade-off between phase noise and spurs.

     

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 20 points
    Thanks Dean!

    that was a very fast and informative repsonse. Thats the info I was looking for - I've been using simple spreadsheets to try and validate phase noise in the lab (including flat and 1/f noise contributions).

    I'm running in both integer, and second order frac mode with no dithering and seeing no change in the noise floor between the two, which now I guess makes sense. However, I've opened up the loop BW to look accurately at the noise floor, and I'm reading a noise floor, which suggests an estimate that the 'flat' PLL figure of merit is more like -219dBc/Hz rather than the -227dBc/Hz I'd expect. This is leading to a 5dB+ degredation in noise floor from where I'd expected it to be. I'm basing this both on the absolute value and also, possibly more importantly, the profile/gradient which (when I look at a corresponding spreadsheet showing individual contributions due to the 1/f and PLL floor, as well as the sum of the two) supports the idea as the gradient due to the 1/f contribution is reduced due to a high flat noise floor in the loop. Noise floor increases as predicted by theory as the RF frequency is increased, and also as the R divider is used to alter the comparison frequency.

    All this is on the eval board with an external VCO (phase noise measured open loop to confirm this is not the issue), and modified third order, type two loop filter. 100MHz Wenzel OCXO as the reference.

    I know its hard for you to comment without seeing the setup and more detail on the loop filter etc, but is there anything obvious I could be doing to degrade the noise floor in setting up the chip?

    Thanks again for your help on this!

    Kind regards,

    Novak