I have an application for the LMX2486/7 with a 10MHz reference clock and 3.5GHz VCO. When I try to set PLL_R = 1 Codeloader forces the value to be 3. When program PLL_R = 1 and update the N, FN, FD for the correct frequency I get much better phase noise than with settings for PLL_R = 3. The data sheet indicates PLL_R value of 1 is valid but Codeloader forces min of 3. Is there some reason for the R register to be forced = 3?
Aaron