Hi,
My customer found strange output from Ftest/LD after short power off. Please see below and give your comment.
[Behavior]
- Ftest/LD output High before setting register so PLL looks locked when Vdd is turned off and on with short duration
[Procedure]
- Power on and set register, then they can confirm desired operation.
- Power off for 1sec and then power on again. at this time the Vdd goes down to 0V absolutely.
- After power on, Ftest/LD pin output High before setting register.
Can you please give your comment why such behavior can be seen after short Vdd turned off?
Best Regards,
Sonoki / Japan Disty