LMX2571 FSK SPI mode -- timing diagram?

Tolchinsky Alexander

In Data Sheet there are no timing diagram and definition of pins for FSK SPI mode. How many bits is transferred on SPI to get to the field FSK_DEV_SEL[4:2] of the register R34? What format of transfer?

Thanks

over 7 years ago

0 Julian Di Matteo over 7 years ago

TI__Expert 4085 points

Hi Tolchinsky,

Thanks for your interest in our products. We received your question. I forwarded this post to the applications engineer that is most familiar with this device.

Regards,
Julian

0 Noel Fung over 7 years ago in reply to Julian Di Matteo

TI__Guru* 81400 points

Hi Tolchinsky,

FSK SPI mode uses the uWIRE interface, Figure 1 in the datasheet shown the timing diagram. SPI programming is 24-bit long.

0 Tolchinsky Alexander over 7 years ago in reply to Noel Fung

Intellectual 290 points

Hi Noel

Thank You, but what format of transfer 24 bits for FSK-SPI? Is it Figure 19 with sequence of bits: RW=0, ADDR_REG34=010_0010, REG34=xxxx_xxxx_xxxS_SSxx (where SSS=FSK_DEV_SEL[4:2])?

What definition of pins - FSK_DV/I2S_CLK(pin 4)=SPI_CLK, FSK_D1/I2S_DATA(pin 6)=SPI_MOSI (DATA), FSK_D0/I2S_FS(pin 7)=SPI_SS# (LE)?

What format of transfer for FSK-SPI-FAST?

0 Noel Fung over 7 years ago in reply to Tolchinsky Alexander

TI__Guru* 81400 points

Hi Alex,

your described SPI programming format is correct, and it is correct for all registers. So for FSK SPI FAST mode, the same format applies.

Pin 4 to pin 7 is the hardware interface for FSK pin mode or FSK I2S mode, it is independent to uWire interface. All registers programming must go through uWire interface (pin 11 to 13).

0 Tolchinsky Alexander over 7 years ago in reply to Noel Fung

Intellectual 290 points

Hi Noel

Thanks for the answer. I got it.

Best regards,
Alexander

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LMX2571 FSK SPI mode -- timing diagram?