Thermal Information at LMV225SD/NOPB

Hello,
I've submitted a request, normal turn time is 2 weeks, I'll see if they can do any faster.

It is worth noting that theta-ja is ultimately an application dependent value. We won't know what the theta-ja is on their PCB.

The value specified in datasheets for theta-ja is for a JEDEC standard test, which is not necessarily what you'll be experiencing in your application. Often it's better in the application. Here's the info for the theta-ja in a datasheet: The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

73,
Timothy

Actually, they did get this info and already had started working on the model, so I now have results.  Please find the info below for LMV225SD, I put in the standard datasheet notes also.  Remember, your theta JA is application specific.

Thermal Metrics (1)
Theta JA-High K (2) = 90.9 °C/W
Theta JC, top (3) = 81.3 °C/W
Theta JB (4) = 60.6 °C/W
Psi JT (5) = 4.0 °C/W
Psi JB (6) = 60.8 °C/W
Theta JC, bottom (7) = 11.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

73,
Timothy