Hello,
I am a researcher at the University of California, Santa Barbara studying the environmental impact of electronic products. One of the ways we model the impact of integrated circuits is by using the silicon die area. Since ICs are encapsulated, we're frequently left to guess the die sizes based on internet searches.
Sometimes we try to X-Ray circuit boards to see the die, but this approach is inconsistent at best, and especially unreliable for SiPs such as Amplifier & RF modules.
I was wondering if it would be possible for someone to tell me the ratio of total silicon die area to package area for some SiP packages? Is there a maximum value for the silicon die area to package area ratio, or perhaps an average value someone could provide?
Thanks!