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Die sizes in SiP modules

Other Parts Discussed in Thread: TPS8268150

Hello,

I am a researcher at the University of California, Santa Barbara studying the environmental impact of electronic products. One of the ways we model the impact of integrated circuits is by using the silicon die area. Since ICs are encapsulated, we're frequently left to guess the die sizes based on internet searches. 

Sometimes we try to X-Ray circuit boards to see the die, but this approach is inconsistent at best, and especially unreliable for SiPs such as Amplifier & RF modules.

I was wondering if it would be possible for someone to tell me the ratio of total silicon die area to package area for some SiP packages? Is there a maximum value for the silicon die area to package area ratio, or perhaps an average value someone could provide?

Thanks!

  • Hello Joseph,

      Sounds like some very interesting work you are involved with.  I wish I could provide a short, concise answer, but nearly every SIP module is designed with its own requirements foremost, not following a standard die-to-module size guideline.  Many of these modules are for dc power, and for example, the TPS8268150 most of the module space is occupied by passive components, not the silicon die: www.ti.com/product/TPS8268150/datasheet/mechanical_packaging_and_orderable_information .

    The RF modules are even more governed by passive components, including the antenna. 

    What might be appropriate is to find some representative modules in each Product family, and evaluate these on an individual basis, perhaps finding a module that has the largest die-to-module ration, and another that has the smallest die-to-module ratio, then find an average.  To your question of whether there is a maximum die-to-package ratio, the answer is no, as this is dictated by the external components required to create an operational circuit.  In general, the module is made to be as small as possible, considering the passive components, interconnects, and heat dissipation. 

    Please let me know your thoughts on this, and any other way we can be of assistance to your investigations.

    At your service,

    ~Leonard 

  • Hi Leonard,

    Thank you so much for the prompt response. I completely agree with the notion that there isn't a single die-to-module ratio. I am, indeed, seeking the average for different classes of SiPs and modules.

    Here's a follow-up question for you: In TPS8268150 (for example), how could I extract the surface area of the silicon die? Those dimensions don't immediately jump out at me from the documentation, but perhaps there's something I am missing.

    Even in the full documentation pdf, it seems I could get the area of the full package and the area of the "pick area", but not that of the silicon die explicitly.

    Is there another part of IC package documentation where I might be able to back out the area of silicon die? Perhaps somewhere other than mechanical & packing information?

    Let me know what you think, and thank you again for your time.

    Best Regards,
    Joe Palazzo
  • Hi Joseph,

      Continuing to use the TPS8268150 as an example, the die is embedded in the pcb material, directly under the inductor.  Since it is not visible, even if the passives are removed, it is not shown on the mechanical drawing.  Coupled with the fact that the die size is proprietary information, it is omitted from the aforementioned mechanical drawing. 

      For this information to be provided, you will have to contact the local TI sales office, initiate and submit an NDA (nondisclosure Agreement) and once approved, the die-size info can be provided. 

      I have not looked at all the power modules, but I'm guessing they will all have the same or similar restrictions for disclosure.  Your local TI Applications or Sales person should be able to assist with this endeavor.

    Regards,

    ~Leonard   

  • Thank you so much! That makes sense to me. Cheers!