This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

AN SCAA880: PLL not locking

Hello all!

I'm trying to implement Application Note SCAA088 to generate a master clock from a I2S source (from a CD player). But I'm having some troubles getting it to work as the PLL is not locking (and thus the output is running freely and not in sink with the input source). This is my schematic:

I've set the output dividers properly to the desired values (Y1 outputs a clock of 44.1KHz, Y2 has half the crystal frequency) and the CDCE913 is configured to operate in VCXO mode. But it seems like the signal from the phase comparator is not arriving properly at the CDCE913. (it's flat zero). when removing the RC-filter, this is what I see on the oscilloscope:

Still no difference in the locking of the PLL however... Does anyone have some pointers for my to try?

  • In reply to Dean Banerjee:

    Hi Dean,


    Thanks for your reply!
    From the datasheet I can't find a way to determine the perceived input frequency. So what would you recommend to do? Use a larger capacitor? What size do you suggest?
    And in case this doesn't solve the issue, are there other things I might try?


    Regards,

    Niek
  • In reply to Niek ten Brinke:

    Niek,

    For the perceived input frequency, it seems this PLL doesn't have a convenient test mode (that I know of anyways). I'm wondering if you were to ground one of the outputs, then maybe you could get some clue of what the device perceived the other output was.

    Also, if there is any way to impact the inputs, maybe this would work. For instance, suppose that the issue was that the CDH74 was counting the second harmonic of the CDCE913 instead of the intended signal. Then sometimes touching the trace (at this works at higher frequencies), or tinkering with R2 might do something. Also in this case, I would expect the circuit to try to drive the CDCE913 output frequency lower, since it perceives it to be too high.

    Regards,
    Dean
  • In reply to Dean Banerjee:

    Hi Dean,

    Alas, I tried increasing the coupling cap to 470nF but still no signal... We've lost hope that this design is ever going to work :(
    Instead, we're going to try and use the SRC4912 to 're-generate' the clock signals...

    Thanks for your help (even though it didn't work out in the end)!

    Regards,
    Niek

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.