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GC4016DK: NO output signals RDY and SFS in parallel mode

Part Number: GC4016DK


I use GC4016 in parallel mode. But I dpn't see output signals RDY and SFS. My sequencing is:

1). Initializing GC4016 Chips

The initialization sequence for a stand-alone GC4016 chip is similar to the one for the multi-GC4016
procedure, except that the ONE_SHOT is used to synchronize the chip, not the SIA input sync. The
procedure is to:
1. Reset the chip by setting address 0, the global reset register, to 0xF8.
2. Configure the rest of the chip, including setting the DEC_SYNC, RES_SYNC, and OUT_BLK_SYNC to
be ONE_SHOT (mode 4) and the OS_MODE to be 1.
3. Assert the syncs by setting ONE_SHOT high.
4. Release the global resets by setting address 0 to 0x08.
5. Release the syncs by setting ONE_SHOT to 0.

2). I write dat to page 98:

page address data

98    16          0xff
98    17          0x40
98    18          0x6c
98    19          0x0
98    20          0xe8
98    21          0x1
98    22          0x0
98    23          0x10
98    24          0x32
98    25          0x45
98    26          0x67
98    27          0x0
98    28          0x2

So after that I don't see signals. Plase tell me what I must do additionally? May be I must check any registers? Thanks.

  • Hello,
    I am not clear if you have a configuration that does not work, or a hardware design you are debugging.
    a) check the VCore and VPad
    b) check the input clock section 4.5
    c) you should use the GC4016 designer kit, or a diagnostic configuration in the datasheet, to help write and read the configuration registers
    page control is very important
    d) when you are about to start the test, and use the One Shot, route the signal to the Sync Out, so you can measure this on the oscilloscope
    e) program the registers in Table 5-13, using the Sync out you should count the number of counter cycles

    f) synchronizing the GC4016 has many stages, they all need synchronization to generate an output
    input (if Zpad is used), Mixer, CIC, CFIR, PFIR, Resampler, Outblock. They usually all need to match OneShot or Never
    make sure the SyncSelect is the desired setting for OneShot or None as appropriate

    g) I usually try to get an output after the Checksum test Table 5-13 passes. section 1.2.8 output modes, using 4 tag bits you can tag which DDC channel is being output. Lets look at Figure 1-16, Par EN, SFS En, RDY En, SFSMode=0, Block Size =3, also check the output clock divider.

    h) so if you get the proper checksum is step e)
    I would reconfigure the output block only, EN_PAR = 1, EN_SFS = 1, EN_RDY = 1, EN_SCK = 1, output mode = 3, master = 1, parllel = 1
    then use the tag bits and rounding to get the channel outputs expected in synchronous mode.

    Joe Quintal