Hi,
SNOA931 stresses the benefits of maximizing the quality factor (Q) of the sensor. For a multi-layer, stretched PCB coil it would thus appear to be beneficial to maintain a sideway offset between the long parallel runs on adjacent layers in order to minimize the inter-layer capacitance (as opposed to "congruent" routes where traces run directly on top of each other which should result in maximum capacitance). Would you agree with this reasoning? Any empirical data on how significant a difference it might make?
Thanks!
