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Part Number: AWR1243
ANA#07 CSI2 Activity Coupling to Clock
Revision(s) Affected: AWR1243 ES1.0 and AWR1243 ES2.0
Description: The activity on the CSI lines during the state transitions at the start and at the end of CSI transfer couples into the clock leading to glitches in the TX output.
Does this show up as a sinusoidal glitch in part of the transmitted chirp ?
Is it coupling from the power lines or from x4 multiplier to the PA ? Additionally is this coupling originating from CSI-2 clock or one of specific CSI data lanes near the CLKP and CLKM on the BGA?
Is this issue only on TX output or does it also impact the LO/IF ?
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In reply to radarJunkie:
In reply to Vaibhav Mahimkar:
In reply to Vivek Dham:
Presently even with external clock there would be slight glitch seen. We will be working on resolving this.
Thank you very much for your response.
You said that even with external clock there will be a slight glitch seen. Is this based on a test or something that team expects given the internal design or layout of the chip ?
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