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IWR1642: Why i can't allocate a bigger size in L2RAM in mmWave DEMO?

Part Number: IWR1642

In 1642 demo, i tried to modify the SOC_AR16XX_DSS_L2_BUFF_SIZE to larger 0x10000 (L2RAM has a 128KB for each UMAP), and the linker will give out an error here.

So what is the limit and how can i modify this?

is L2RAM proccessing faster than L3RAM? So is it possible to move some variable or array (e.g. detmatrix) to L2RAM from L3RAM in the DEMO?

  • Hello,

    Thank you for your interest in our device!
    This ticket has been assigned to expert and they will soon respond here.

    Regards,
    Vaibhav
  • Hi,

    Description of the C74x internal memory is found in the C74x TRM, (search for SPRUH91D on ti.com).  The C74x has 256K L2 RAM.  This is configured as described in section 4.2 of the TRM as partly cache and partly RAM.  The RAM portion is further divided by the demo's BIOS config file (dss_main.cfg) which allocates 16KB of L2 for heap.  The linker config file divides it into two halves:

    (from SDK 1.0.0.5)

      L2SRAM_UMAP1          007e0000   00020000  00020000  00000000  RWIX
      L2SRAM_UMAP0          00800000   00020000  00016d19  000092e7  RWIX

    So it seems that it is all configured as RAM.  The failure you are seeing is because a block of 0x10000 will not fit with what is already configured.

    The #define SOC_AR16XX_DSS_L2_BUFF_SIZE is from SDK 0.8.  In the 1.0.0.5 SDK, the name has changed to MMW_L2_HEAP_SIZE and is set to 0xC000, up from 0x5000.

    And yes, L2 RAM will be somewhat faster than L3.  L2 typically is accessed at the CPU's clock rate, with no divisions.

  • In reply to db_woodall:

    Hi, since there's been no response in about a month, I will close this ticket. If you have another question, please open a new one.