• Resolved

AWR1243: ANA#07: Errata Silicon SWRZ071

Part Number: AWR1243

Hi, 

ANA#07 CSI2 Activity Coupling to Clock

Revision(s) Affected: AWR1243 ES1.0 and AWR1243 ES2.0

Description: The activity on the CSI lines during the state transitions at the start and at the end of CSI transfer couples into the clock leading to glitches in the TX output.

Does this show up as a sinusoidal glitch in part of the transmitted chirp ?

Is it coupling from the power lines or from x4 multiplier to the PA ? Additionally is this coupling originating from CSI-2 clock or one of specific CSI data lanes near the CLKP and CLKM on the BGA?

Is this issue only on TX output or does it also impact the LO/IF ?

Thank you,

RJ

  • Is there a fix in place or planned for this in the production version of AWR 1243 ?
  • In reply to radarJunkie:

    Hello,

    Thank you for your interest in our device!
    This ticket has been assigned to expert and they will soon respond here.

    Regards,
    Vaibhav
  • In reply to Vaibhav Mahimkar:

    Hello RJ,
    The glitch due to the CSI activity is observed when the CSI data lanes transition between the LP and HS modes as per the MIPI protocol. This transition happens at the beginning and end of the packet transfer over CSI.
    We do plan to fix this in the production silicon . For now the work around can be to increase the chirp idle time such that the complete ADC data gets transmitted out over CSI within the idle time and does not extend to the next chirp. This way the LP/HS transmissions will happen at time when the ADC is not sampling any data and would not cause any glitch in the ADC data.

    Regards,
    Dham
  • In reply to Vivek Dham:

    Thank you so much Vaibhav and Dham !

    Dham: I appreciate the detailed response. I understand better now when the glitches happen in respect to the MIPI protocol. Great to hear that this will be fixed in production samples. I am still trying to understand the nature of the coupling.

    Does this coupling only impact the 76+ GHz Tx output or does the coupling also impacts the LO signal ? Additionally is this coupling originating from CSI-2 clock or one of specific CSI data lanes near the CLKP and CLKM on the BGA?

    I appreciate your promptness and support.

    Regards,

    RJ
  • In reply to radarJunkie:

    Hello RJ,
    The impact is on the LO, hence we see it on the TX output. The source of the glitch are the data lines (both the lanes).

    Regards,
    Vivek
  • In reply to Vivek Dham:

    Hello Vivek,

    Thank you once again for your reply. I appreciate it.

    I understand that AWR1243 is targeted towards cascade architectures.

    As an example if one AWR1243 was used as a master only (not acting as a receiver, not sampling adc data) and sent LO signals to two more slave AWR1243 devices in star topology (total of 3 chips) plus other sync signals.

    In this situation, will the coupling issue still manifest itself in the IF data of the slave AWR1243s ?

    Thank you and appreciate your help :)

    Regards,

    RJ
  • In reply to radarJunkie:

    Hello RJ,
    That's an interesting question ! We have not tried this exact scenario since most likely one would like to use the master for chirping as well apart from providing the LO. Let me check a bit more on this and get back.

    Regards,
    Vivek
  • In reply to Vivek Dham:

    Hi Vivek,

    Did TI see this problem when the in-house cascading prototype was developed with AWR 1243 ? and then had to implement the same work around ?

    Thank you,

    RJ
  • In reply to radarJunkie:

    Hello RJ,

    Presently even with external clock there would be slight glitch seen. We will be working on resolving this.

    Regards,

    Vivek

  • In reply to Vivek Dham:

    Hi Vivek, 

    Thank you very much for your response. 

    You said that even with external clock there will be a slight glitch seen. Is this based on a test or something that team expects given the internal design or layout of the chip ?

    Regards,

    RJ