If we are using more than one AWR1243 ICs in a cascaded mode, can we use one SPI bus to address all of the AWR1243 ICs sequentially by selectively asserting the CS pin? That is, can all the AWR1243 ICs share the same CLK, MOSI signal lines from the microcontroller, and Logic-OR their Host_Intr lines together into the microcontroller, and multiplex their MISO lines? We are trying to minimize the number of wires between the microcontroller and the AWR1243 ICs.
Thank you.
mmWaver