AWR1642: Is possible to connect a general SPI flash on QSPI interface?

Hello Omin,
We have validated Spansion, Micronix, Winbond SDF .
But typically , the SDF that supports Quad mode and JEDEC commands should be possible to use.

Thanks,
Raghu

Hello Omin,

There are the following factors that will determine if the XWR16xx ROM bootloader will be able to interface and work with the SFLASH on XWR16xx devices:

Pre-requisite:
SFLASH supports the SFDP command and responds with JEDEC compliant information regarding the capabilities and command set of the flash.

ROM assisted download to the FLASH (Device Management mode - SOP5):
 The ROM assisted download should work with all flash variants that allow for “Memory mapped mode” and “Page program command (0x2)” with 1 dummy byte and 24bit addressing.
 In addition to writing to the Flash, the ROM bootloader also support setting the “Quad Enable” bit for Spansion and Macronix variants (certain specific part variants only).
In case any of the above steps fail, the device supports “Boot mode – UART” which can be used to download an application onto the MSS RAM and execute, which can be used to program the SFLASH.

ROM based load from FLASH (Functional mode – SOP4):
The ROM bootloader performs the read from the FLASH based on the highest capability mode (Quad/Dual/Single) as published by the SFLASH in response to the SFDP command. The commands used also are as published by the SFDP response. So if the Quad read is supported, the expectation is that the Quad Enable (QE) bit is already set in the FLASH. The ROM bootloader would use the Quad mode to perform the read.

Recommendation:
The flash vendors have an orderable part variant with the Quad Enable (QE) bit set. It is recommended to use these variants to work with TI mmWave SOCs.

Known Issues:
The ROM bootloader in XWR1642 pre-production devices in not compatible with SFLASH variants that support extended addressing mode. In particular, the “Number of Address length” field of the SFDP command response being non-zero is not supported. The total SFLASH addressable region in XWR1642 devices is 8 MBytes. So “Number of Address length” = 0 (corresponding to 3 bytes address length) will satisfy the addressable range. However, the compatibility issue is with variants that allow for “3 or 4 bytes address length”.
This incompatibility will be addressed in our production version of the XWR1642 silicon.

Hope this helps!

Best regards,
Naveen

Hi Naveen,

Thanks so much for your detailed explanation.

After double checked IS25LP032D spec, it supported SFDP command with standard of JEDEC JESD216. And also supported Quad Enable bit set.

My hardware connection should be as below. Please help to double confirm that is ok to work with AWR1642.

AWR1642 QSPI Interface	IS25LP032D
QSPI_CLK (R12)	SCK
QSPI_CS (P11)	CE#
QSPI_0 (R13)	SI
QSPI_1 (N12)	SO
QSPI_2 (R14)	WP#
QSPI_3 (P12)	HOLD

Thanks in advance.

B.R.

OC

Hi Omin,

Yes the HW connections are correct!
Please ensure that there is a pull (pull_up) applied on the QSPI_2 and QSPI_3 pins. You may use the TI EVM schematics as reference.
Further, please ensure that the Quad bit is already set as the ROM bootloader will expect that the bit is set and attempt the Quad read.

Best regards,
Naveen