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IWR1443BOOST: traces length question of IWR1443Boost layout

feng tang
Genius 3595 points
Part Number: IWR1443BOOST

The checklist says "

The SPI interface lines (SPI CLK , MOSI , MISO, SPI_CS, HOST_INTR) should be length matched (<200 mils mismatch) to enable 40Mhz data rate.

The traces length on IWR1443Boost layout (E2) not meet this requirement, why?

AR_MISO1 routing length 2099 mils

AR_MOSI1 routing length 2528 mils

AR_HOSTINTR routing length 2597 mils

AR_QSPI_CS routing length 1244 mils

AR_SPI_CLCK routing length 1758 mils

Does this impact the performance?

How they should match each other?

  • 0
    TI__Guru 50240 points
    Hello Feng,

    I've referred your question to our hardware expert who should have an answer for you either today or tomorrow.


    Cheers,
    Akash
  • 0 in reply to Akash Gondalia
    TI__Mastermind 37500 points
    Hello Feng
    The initial xWR mmwave sensor EVMs the QSPI interface was 4Mhz. ES2 devices have an 18Mhz SPI clock. ES3 devices have a 40Mhz SPI clock.
    The skew tolerance should be based on < .5ns skew between QSPI_CLK, and QSPI_CS, QSPI_Data[4].

    Host Interrupt is a door-bell CMOS signal generated by the mmwave sensor, and received by the Host Processor. Since its a slower signal, non clocked, it doesn't have a skew tolerance.

    The SPI port SPI_CS, SPI_CLK, SPI_MOSI, SPI_MISO routing is based on a 40Mhz SPI_CLK, having < .5ns skew. If you Host processor is initialiting the SPI at a slower clock rate, then the matching can be adjusted.

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Genius 3595 points

    So your schematic does not match your Layout, your schematic that give to us is 40 MHz which is ES3, your layout provide to us is ES2, is this true?

  • 0 in reply to feng tang
    TI__Mastermind 37500 points
    Hello Feng,
    The schematic has not changed from ES1 - to - ES2 - to ES3. The initial layout has also not changed.
    The rules are based on the current clock rates. If you look at the current QSPI parameters, the .5ns margin
    allows you to meet 40Mhz QSPI timing.

    Most Host MCUs will limit SPI speed to ~16Mhz, there is no Host MCU on the EVM.

    The Layout is based on initial ES1 devices.

    Regards,
    Joe Quintal