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AWR1243: number of questions regarding automotive RADAR

Part Number: AWR1243
Other Parts Discussed in Thread: TDA2

Dear team,

My customer has the following questions regarding automotive RADAR:

 

1. what the best power management for a TDA2x family processor + AWR1243P RF front end.

there are schematic with LP87524, but according to the  " http://www.ti.com/processors/automotive-processors/tdax-adas-socs/applications/radar.html "

the recommendation is  

TPS65917 or TPS659039

 

2. there are a 2 Band Width types, the first is sweep BW =4GHz and second is IF = 15MHz. I can't understand what the purpose of IF band? what is added value of 15MHz, 20MHz is better?

 

3. At cascading mode, 4 AWR1243 (3 slaves and 1 master) we have a 4 MIPI CSI bus, but TDA2X process have only a 1 MIPI input, there is some FPGA that convert 4 MIPI to VIP bus? could you send me some schematic or block diagram, please?

 

4. please send me a full datasheet of AWR1243 that include information about output power of FM_CW_CLK_OUT signal, according to some reference schematic this is 6dBm, but is not exist in the datasheet

Can you please advise for the above, Thanks a lot.

Kind regards,

Shai

  • Hi

    We are checking with our team about availability of this information

    Thank you
    Cesar
  • Hello,
    1. The power management for a TDA2, follows the TDA2 EVM. The AWR1243 in Cascade architecture (meaning 2 devices) would use the LP87524J device with 2nd stage LC filters discussed in swra577. If you have 4 AWR1243, you would have (2) LP87524J devices. Depending on your desire for better power supply efficiency vs load regulation, you would use swra577 with 2nd stage LC filter for better efficiency. If you are more interested in 1.0v noise, you would change the BUC2 output to 1.3v, and have an RFLDO with 2.5A per AWR1243, probably with an output filter per device.

    Note: there is an I2C port, PMIC_Int GPIO, and PMIC_Enable GPIO from each LP87524 device. If there is more than 1 LP87524, you will need another I2C port or switch, if they have a common I2C address.

    There is an Automotive TDA processor and 4 AWR1243 cascade 2 board EVM to be released 3rd-4th quarter that will have a reference design. Check the AWR1243 TI page for release announcement.

    2. In the FMCW receiver the reflected off of target signal is delayed in time. The detected time delay is 2x the distance at the speed of light. Since the Synthesizer 76-81Ghz signal is the Transmit, and Complex Receive mixer Local Oscillator, the IF output of the mixer is proportional to the 2x distance (time) * synthesizer slope. If the synthesizer slope is 40Mhz / usec, a .2usec delay, results in a 8Mhz frequency output from the mixer.

    The synthesizer has a stabilization delay, a time for the ADC sampling, and an excess time to insure linearity. The range of the synthesizer (related to Tx output) is 76-77Ghz or 77-81Ghz. In my radar cycle, the amount of time the signal reflects off the target helps us to detect the reflection.

    After the Complex Mixer there is a High Pass Filter (densensitize close objects) ADC filter, ADC, and a Digital Front End that filters, decimates, and converts to real, complex 1x, or complex 2x rates. The complex 1x, covers the 0IF to DFEout (max 18.75e6), the filtering is 90% passband.

    Lets say that we have 10Msps DFE output, the chirp has 512 samples, the stabilization delay is 7us, the excess time is 1us. The chirp active cycle is 51.2us+7us+1us = 59.2us. The synthesizer slope of 40Mhz/usec, 2.368Ghz over cycle.

    Why does the slope of 1-100Mhz/usec help. The faster that we change frequency, the higher the detected frequency difference.
    range = (c0 * dT)/2 = (c0 * dF)/(2 * dF/dT) range resolution is better if the slope frequency is higher. Also if you want a longer range, eventually the IF frequency is lowered, by lowering the slope.

    The swra553 document discusses the Radar Equation and Chirp / Frame parameters.

    3. The new Cascade reference design has a CSI2 to VIP bus that is an FPGA.

    4. The new AWR1243 ES3 device will have the RF 76-81Ghz, and the FMCW Synthesizer 19-20.25Ghz. The new datasheet is scheduled for release 3Q with the AWR1243 ES3 device Product Launch. The datasheet is being worked on.

    Regards,
    Joe Quintal
  • Joe,
    thank you for this info.
    but still dismissed explanation about BW sweep (4GHz) and IF BW (15MHz).
    can you please elaborate more on both aspects.

    Thanks
  • Hello 

    The IF bandwidth allows for the DFE signal difference in the complex mixer to be passed to the digital infrastructure.  The decimating low pass filter, and Complex 1x frequency shift are the detection range of the FMCW radar.  

    When you use the radar equation, see swra553, to develop a sweep profile, and then select the DFE output rate.  This limits the range of detection.   

    As an example, if the FMCW slope is 10Mhz/usec,   if the DFE output rate is set to 6.25Msps, with 80% passband, we can only have signals of interest for Complex 1x mode from 0 to 5Mhz.  The  range based on this slope and DFE sample rate is DFEoutrate / slope

    reference" www.radartutorial.eu/.../Frequency Modulated Continuous Wave Radar.en.html   "

    IF = (complex 1x mode) .8 * DFEoutrate

    Range = c0 * IF/(2 * slope)

    3x10e8*5e6/(2 * 10e6/10e-6) =  300meters

    the overall chirp time, is the DFE output rate * numADC samples in the chirp

    the frequency difference the FFT has is based on the FFT size, for range resolution (detecting multiple objects we need a lower frequency/bin value)

    using the largest standard FFT size 1024, we can simplify the chirp programming by using 1000 DFE output samples.

    the synthesizer has an ADC/DFE setup time, a chirp time, and an excess chirp time.  The 4Ghz range limit is based on the amount of time the synthesizer is sweeping, if we had a smaller range limit the chirp time, or slope would need to be reduced.

    1000 samples / DFE out rate (6.25e6) = chirptime = 160us = active_chirp_time

    ADC/DFE setup time = 7us, excess chirp time = 1us, so the total sweep time of the synthesizer is 168us for this example.  

    Given a synthesizer_slope of  10Mhz/usec, if the Synthesizer start frequency is 77Ghz, the end frequency is 77 + 1.68Ghz.

    range resolution = c0/(synthesizer_slope * active_chirp_time * 2) = 9.3cm

    the range resolution improves based on the synthesizer slope, active chirp time.    The IF bandwidth relates to the maximum range (time) that can be processed.

    Note: the FMCW radar can have multiple chirps for short and long range.  The swra553 has examples for Short and Long Range radar.

    Regards,

    Joe Quintal

  • Dear Joe, Thank you very much for the detailed answer.

    Kind regards,
    Shai
  • Hello Joe,

    I do have an additional question is regards HPF :

    what the purpose of these filters HPF1 and HPF2?

    Thanks in advance

    Kind regards,
    Shai

  • Hello,

    The HPF1, and HPF2 High Pass filters reduce the radome, bumper, close-in reflection by attenuating low frequencies after the Downconversion Mixer.

    Regards,

    Joe Quintal