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AFE4403: Question about PDNCYCLE

Nicky Lim
Genius 3195 points
Part Number: AFE4403

Hello,

Customer wants to make minimum use of LED by PDNCYCLE, but LED is not controlled with AFE4403EVM test.
Is PDNCYCLE able to make power down only internal block except LED?

So, customer wants to make LED ON only during LED가 ADC capturing by using CONTROL2 PDNTX bit ON/OFF.
At this time, Ramp Up time is not needed or need min. 50us delay as below in datasheet?

Datasheet : TI recommends setting t1 > 50 μs and t2 > 200 μs in order to ensure sufficient time for the shutdown blocks to recover from power-down

And could you recommend delay time for accurate data acquisition below each condition.
1. PDNTX bit on/off ==> ??
2. PDNTX/PDXRX on/off ==> ??
3. PDNAFE on/off ==> more than 1s (in 7.7 Timing Requirements: Supply Ramp and Power-Down)

Regards,

Nicky

  • 0
    Genius 3195 points
    Hello,

    Is there any update?

    Please let me get your reply ASAP

    Thanks & Best Regards,
    Nicky
  • 0 in reply to Nicky Lim
    TI__Genius 12555 points
    Hi Nicky,

    Sorry for the delayed response.

    In AFE4403 if you want to control the TX block dynamically based on the PDNCYCLE, you have to write DYNAMIC1 bit in CONTROL2 register.
    Bits such as PDNTX, PDNRX, PDNAFE are the static controls and do not depend on PCNCYCLE signal.
    So I suggest to use DYNAMIC1 ( also other DYNAMIC bits) with the PDNCYCLE to save power dynamically.

    Regards,
    Prabin
  • 0 in reply to Prabin Yadav
    Genius 3195 points
    Hi Prabin,

    Could you let me get the answer about each delay time, also?

    And could you recommend delay time for accurate data acquisition below each condition.
    1. PDNTX bit on/off ==> ??
    2. PDNTX/PDXRX on/off ==> ??
    3. PDNAFE on/off ==> more than 1s (in 7.7 Timing Requirements: Supply Ramp and Power-Down)

    Regards,
    Nicky
  • 0 in reply to Nicky Lim
    TI__Genius 12555 points
    Hi Nicky,

    As mentioned in datasheet under "Timing" section of "Electrical Characteristics" (i.e. Pg. no 9), the delays are as given below.
    PDNTX bit on/off ==> 1S
    PDXRX on/off ==> 100uS
    PDNAFE on/off ==> 1S

    Regards,
    Prabin