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AFE4403: Interfacing with multiple AFEs over SPI

Robert Marosi
Prodigy 50 points
Part Number: AFE4403

Hi all,
I'm planning to interface a single-board computer with 8 AFE4403's over SPI. The SPI bus will be in a star configuration with each of the slaves separated from the master by up to 15cm of cable.

1. Is it possible to daisy chain the SPI data lines so I can free up some GPIOs that would be used for a 3-to-8 slave select decoder? The AFE44xx datasheets do not specify such a capability, but I figured it might be worth asking anyway.

2. Due to the distances and number of devices loading the bus, is it recommended to use some sort of buffering and/or terminations on the SPI bus? What components and/or design schemes do you recommend?

3. In the event that I cannot source a low-jitter (<50ps) clock output from a single-board computer and have to resort to having crystal oscillators on each AFE, how will this affect communication between the AFEs and the processor? I am considering clocking the SPI bus at 1MHz. I am also planning to average the ADC samples as much as possible with the AFE.

Thanks,

Robert

  • 0
    TI__Mastermind 49176 points
    Hi Robert,

    We have received your inquiries about system challenges in interfacing multiple AFE4403s.
    Regarding question #1, it is not possible to daisy-chain the SPI data lines.
    We will get back to you on your other questions shortly.
  • 0
    Prodigy 50 points
    I just noticed that the timing requirements of the AFE4403 demands that the SPI clock be at least 16MHz, not 1MHz. This sounds too "hacky" to work, but would it be feasible to leave the SPI clock running at 16MHz and tie it to the external clock pin of the AFEs?
  • 0 in reply to Robert Marosi
    TI__Genius 12555 points
    Hi Robert,

    I am very sorry for the delayed response.
    There is a section in the AFE4403's datasheet called "Digital Signal Characteristics" (page no 9) that specifies the signal levels for the digital pins. So as long as your single board computer is able to provide those levels over the given trace wire, you can connect multiple AFEs without any buffer, otherwise you have to use buffers.
    If you want to synchronize all the AFEs, you have to given a common clock. However if the AFEs are supposed to be independent , then each of them can have their own clock.
    Even though the datasheet specifies 16MHz as minimum clock for SPI, you can use the lower clocks as well.

    Regards,
    Prabin
  • 0 in reply to Prabin Yadav
    Prodigy 50 points

    Hi Prabin,

    Thank you for your answers to my questions. I will keep those signal level requirements in mind when experimenting with the AFEs. If I end up needing to clock the AFEs independently of the SPI bus master, do you know if there be might any potential risks such as glitches on reading/writing to the AFEs as consequence?

    Thanks,

    Robert

  • 0 in reply to Robert Marosi
    TI__Genius 12555 points
    Hi Robert,

    I don't think there will be any glitches as long as you SPI signals are proper. Having a multiple SPI clocks for multiple AFEs should not create a trouble.

    Regards,
    Prabin