This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDC118: DOUT output format and Timing issue

Part Number: DDC118
Other Parts Discussed in Thread: CC3200

Hello,

I am having some difficulties understanding the output format for the DOUT Pin on the ddc118.

Here is my Setup. I am using a TI Launchpad CC3200 as my master micro-controller. It is generating the following data.

  1. Output Pins
    1. CLK speed = 100KHz
    2. DCLK speed = 50KHz
    3. CONV = 500us
    4. TEST Pin is held high and probed twice with 5us pulse widths to generate 22pC from the ddc118. 
  2. Input Pins
    1. DVALID' (active low). I poll this pin in a while loop to know when the ddc118 pulls the pin low. 
    2. MISO. I am using an SPI interface where I connect the SPI Clk into DCLK and MISO to DOUT to read the output data from the ddc118.

I am attaching two screenshots to demonstrate my power-up sequence and the output format of DOUT after the 10th CONV cycle. 

Here is my power-up sequence with the following initial values.

  • FORMAT = '0b' (16-bit output)
  • RANGE = '111b'
  • HISPD/LOWPR = '1b'
  • CLK_4x = '0b'
  • TEST = '1b'
  • CONV = 500us
  • CLK = 100KHz
  • DVALID = 'active low' (when data is ready)
  • DOUT = 'output format'
  • The screenshot starts as soon as I pull RESET low to restart the ddc118 then I wait for 30ms to apply the pins listed above.

Here is a screenshot of the 10th CONV cycle.

  • It is more clear in this screenshot how RESET, TEST, CONV, CLK, DVALID, DCLK, and DOUT Pins are behaving, but I am not understanding the output of DOUT. 
  • From my understanding of the datasheet.
    • A 22pC input charge would translate to a 0x1017 hex value, but instead I am seeing 0x0106 hex coming from DOUT.
    • I need to clock DCLK with 128 (16 bit x 8 channels) falling edge bits (since FORMAT  = '0b' which implies 16 bit output per channel) in order to shift out every bit of each input channel starting with the MSB of channel 8-to-LSB channel 8, repeating for Channel 7, Channel 6, Channel 5, Channel 4, Channel 3, Channel 2, and finally Channel 1.

 

  

Can someone help my understand the output format of DOUT or if my timing is incorrect? 

Thank You.

  • Hello Alejandro,

    Welcome to TI E2E forum!

    We have received your inquiry about the device DDC118 and will get back to you by 10/20.
  • Any headway on this issue?
  • Hi Alejandro,

    If you refer to Table 6 of the DDC118 datasheet, it provides the number of clock cycles for the conversion times and when the data will be ready.
    With 100KHz CLK, the conversion takes about 13.8 ms and that is the reason why you are getting the first DVALID signal after about 15 ms.

    Is there any particular reason for providing slower clock and data clock?
    Can you provide 4MHz to CLK and DCLK and check for the data on DOUT?
    With 4MHz CLK, the time for data ready would be 345 us.
    With 500us CONV time, the data should be available at ~345 us after every CONV edge.
  • I went ahead and implemented your suggestions. I am now able to read the appropriate values for an 11pC, 22pC, and 33pC Test input charge, but I have a question. Hopefully you can guide me in the right direction.

    My original assumption was that I would see the respective Test input charge across all ‘8 inputs’ as each data-word is shifted out during the retrieval process on DOUT. I understand that the Test Pin disconnects all of the ddc118 analog inputs (IN1 thru IN8), but according to the datasheet “Each rising edge of TEST causes approximately 11pC of charge to be transferred to the integrators” which leads me to believe that I would see the same respective Test charge for every data-word shifted out of DOUT for that given CONV cycle. Currently, I only see the Test input charge for the first data-word and a zero value for the remaining seven other data-words. Is this a valid assumption or will I only read the Test charge on just the first data-word?

    If you analyze the images in my first post you will notice that DCLK has a small gap in between each data-word (16 bits) which comes from a limitation of the cc3200 SPI module. I suspect this small gap is invalidating the data retrieval process after the first data-word on the ddc118, but I could be wrong.

    I have read and search for many posts on how to provide a continuous many-byte long data transfer over the cc3200 SPI module with varying success. I do have the SPI Module configured with “SPI_TURBO_MODE_ON”. From your knowledge will the small delay between each data-word invalidate the retrieval process? Would you have any guidance or resources for me? Any would be appreciated.