Other Parts Discussed in Thread: PGA900
Tool/software: Code Composer Studio
Hi.
I have done a prototype PCB design with the PGA900. When I apply supply voltage between I measure VDD to 3,5V, so I know that the Gate Ctrl at least works.
In Code Composer Studio when I run the Connection Test for my Target Configuration file the XDS200 successfully reads the IDCODE register.
-----[Perform the SWD Mode Integrity test]-----------------------------------
This test will read the IDCODE register 100 times.
The IDCODE register value is 0x0bb11477.
The SWD Mode Integrity test has succeeded.
[End: Texas Instruments XDS2xx USB Debug Probe_0]
So I assume this means that I should be able to run my code on the target.
However, when I connect to Target and try to load the output file I get this error message.
Cortex_M0_0: File Loader: Verification failed: Values at address 0x0000000000000B40 do not match Please verify target memory and memory map.
Cortex_M0_0: GEL: File: Z:\workspace\firmware_00\Debug\PGA900.out: a data verification error occurred, file load failed.
I read somewhere that maybe the GEL file needs to be modified when going from the Evaluation Module to an actual design. I don't feel I have the insight to know if this is true much less what to adjust.
Any tips?
-Esben