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AFE5818: Determinisic latency

Alex Zabrovsky
Prodigy 170 points
Part Number: AFE5818

The quesiton focuses the AFE5818, however is generally related to high-speed ADCs with LVDS outputs.

I keep noting in various articles that LVDS-type ADC does not support deterministic latency (hence may pose troubles to synchronize several of such devices)

However, AFE5818 as an example of such, there is known parameter as ADC latency (8.5 device clocks by default unless configured for low-latency mode allowing 4.5 clocks).

If this parameter is known ahead - why it is considered non-deterministic ? Lets say having 10 of such devices in the system that need to be synchronized to each other.

If the ADC latency is known ahead, the effort to achieve multi-device sync is just to properly layout the PCB with ADC Clock to be distributed in-phase to all and take care to route LVDS outputs allowing aligning of timing delays (length match + impedance). What is non-determinisic here ?

Would appreciate for clarification of the matter

Thanks, Alex

  • 0
    TI__Expert 4145 points

    Hi Alex,

    Please look at Page 21 of the datasheet for the device's detailed LVDS output timing diagram.

    In addition to the ADC latency (Cd) you stated above, there is a propagation delay (tpdi) which varies from device to device. This is one reason why it is considered non-deterministic. 

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    Prodigy 170 points

    Thank you

    The datasheet defines the tpdi parameter as a function of td (data bit duration) and this parameter is deterministic (as is function of fD which is in turn deterministic once serialized rate is defined)

    If so, why this is expected to vary from device to device (given several devices are configured for teh same output bit rate) ?

    Please advise

  • 0 in reply to Alex Zabrovsky
    TI__Expert 4145 points

    Hi Alex,

    That formula for tpdi represents a "typical value" for the delay from input clock to output frame clock. What we see is a few ns variation in this clock propagation delay from device to device.

    This is why we recommend deserializing each AFE with its own frame and bit clocks as the variations in propagation delay means that for the same input ADC clock, different AFEs will have slightly out-of-phase frame and bit clocks (and data). A common system clock can then be used to synchronize the deserialized parallel data for further processing.

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    Prodigy 170 points

    Yes, thank you, now it is clear what the reason behind the LVDS ADC device providing both LVDS frame and bit clocks. (Usually regular, general LVDS provides frame clock only and the receiver recovers bit clock based on input frame clock serialization parameters)