AFE5818: AFE5818 LVDS differential routing pin delay / internal wiring length

Hello Vassili,

We have received your query about the differential routing of LVDS data and ADC clock and shall get back to you with a response soon.

Hello Praveen,

Besides delay between N and P within the same pair, the question is also relevant for delay between different pairs.

Can I assume that row U has delay 2*0.8mm vs row U, and row T has delay 0.8mm vs row U?

Best Regards, Vassili

Hi Vassili,

Figure 108 only shows one end of the traces for DOUTx4. The picture below shows how the traces are compensated via routing to match in length.

Sincerely,

Olu

Hi Olu,

Basically you are telling me that

1. All LVDS pins of AFE5818 have the same package delay and both traces for each DP (differential pair) must have the same length.
2. Layout on Fig 108 produce dynamic phase mismatch of ~ 0.8mm, which is compensated on other side of DP trace, instead of immediate compensation next to AFE5818, as described in TI High-Speed Interface Layout Guidelines section 2.3 High-Speed Signal Trace Length Matching, Fig 5?

My conclusion: I should compensate phase mismatch close to AFE5818? Please advice?

Best Regards, Vassili

Hi Vassili,

I agree with your conclusion.

Sincerely,

Olu