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HDC2010: I2C timing requirements

Shu-Cheng LIN
Guru 11785 points
Part Number: HDC2010

Hi Sirs,

Sorry to bother you.

Because HDC2010 I2C datasheet  timing requirements information are not clearly. 

So could you help confirm  HDC2010's I2C is compliant with the I2C standard spec (UM10204) and is backward compatible with Standard-mode (100bits/s)?

Thanks!!

  • 0
    TI__Guru* 91086 points

    Dear Shu-Cheng - 

    Please see page 6, section 6.7, parameter fSCL which is specifies the device operates over I2C bus from 10kHz to 400kHz. 

    http://www.ti.com/lit/ds/symlink/hdc2010.pdf

  • 0 in reply to Josh Wyatt
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    Actually we mean that the HDC2010 I2C timing shows too few parameters.

    Since my MCU uses I2C Standard-mode (100Kbits/s), Could we refer to the more detailed I2C standard spec (UM10204) when measuring all time parameters of SCL/SDA?

     For example, rise time & fall time, We only need to follow the standard-mode in the I2C spec? Because there is no minimum limit for these two times.

     For the same reason, other time parameters, tLOW / tHigh... parameters, only refer to Standard-mode (100Kbits/s), do not need to see Fast-mode (400Kbits/s)?

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 91086 points

    Dear Shu-Cheng - 

    For the rise time, this is a system level requirement. Please see  (in I2C spec) - the important value is the one spec'ed its practically impossible to have 0 rise or fall time, especially when there is known RC time in the circuit. Are you or have you measured a short rise (which is again a system level topic) or you are seeing that the part cannot meet some fall time your MCU expects? (this would be odd)

    Section 5.1

    The external pull-up devices connected to the bus lines must be adapted to accommodate
    the shorter maximum permissible rise time for the Fast-mode I2C-bus. For bus loads up to
    200 pF, the pull-up device for each bus line can be a resistor; for bus loads between
    200 pF and 400 pF, the pull-up device can be a current source (3 mA max.) or a switched
    resistor circuit (see Section 7.2.4).

    And Section 5.2 (which mentions the times for Standard mode in the typical context)

    The drivers in Fast-mode Plus parts are strong enough to satisfy the Fast-mode Plus
    timing specification with the same 400 pF load as Standard-mode parts. To be backward
    compatible with Standard-mode, they are also tolerant of the 1us rise time of
    Standard-mode parts. In applications where only Fast-mode Plus parts are present, the
    high drive strength and tolerance for slow rise and fall times allow the use of larger bus
    capacitance as long as set-up, minimum LOW time and minimum HIGH time for
    Fast-mode Plus are all satisfied and the fall time and rise time do not exceed the 300nSec tf
    and 1 uSec tr specifications of Standard-mode.

     

     

  • 0 in reply to Josh Wyatt
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    Our MCU I2C is set to 100Kbis/s according to Standard-mode.

    The actual measurement on the circuit is SCL & SDA fall timing < 6ns.

    According to the Standard-mode specification, there is no minimum time limit for tf, there is no problem with the specifications.

    However, according to the I2C Fast-mode specification, tf >12ns: 20*(3.3V/5.5V) is out of specification.

    Since HD2010 does not have a detailed I2C timing requirement, so we want to determine if this tf < 6ns is allowed in the HDC2010 I2C or not?

     

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 91086 points

    Shu-Cheng - 

    You calculated your pullup resistors to conform to the rise time of the I2C spec, correct? This is the more important parameter I think

    do you have any measurements - would look like this, with the large values (68k to 6.8k being examples of extreme)

  • 0 in reply to Josh Wyatt
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    Could you help check if tf < 6ns this spec could meet HDC2010 I2C allowable range?

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 91086 points

    Dear Shu-Cheng - 

    i can check this out - but I am not sure you got the point I was making about what really matters here. Why is it so important to you regarding the fall time, when the rise time is the critical thing to worry about? Have you seen any issue with this in your testing, have you actually captured a fall time this fast, or this is hypothetical question? 

    Which MCU are you using?

  • 0 in reply to Josh Wyatt
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply,

    The waveform please refer as below.

    The actual measurement SCL fall time is less than 6 ns.

    There are same result for different oscilloscope measurements.

    Is this within the HDC2010 I2C tolerance range?

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 91086 points

    Dear Shu-Cheng -

    the images did not make it onto this post, if you meant to insert or attach. 

    please try that again - 

    which MCU are you using? Have you seen any issues with this so far? Did you already fix the pullup resistors to make the rise time correct?  

    did you try already a resistor in series with the SCL line, near the MCU?

    Here you are asking if our device will accept an MCU which you have measured in your system, that is operating out of spec - while we do generally test devices to the limits and sometimes beyond, we try to follow specifications (like the I2C one) as much as possible to ensure interoperability. As a rule we will not make a statement that we accept out of spec behavior - if this is a requirement for your system to meet the spec, I suggest you add a series resistor to the design which slows down the SCL fall time to between 12 and 250nSec and continue on your path towards release of your design.  

  • 0 in reply to Josh Wyatt
    Guru 11785 points

    Hi Sirs,

    Please refer  waveform as below.

    Thanks!!

  • 0 in reply to Shu-Cheng LIN
    Guru 11785 points

    Hi Sirs,

    MCU : Nordic nrF52840,     

    SCL rise time = 112ns, less than 1000ns is within the spec range, should not need to consider the rise time. Has finished high and low temperature test, although the system can work stably.
    But I2C of the MCU is 100Kbits/s, and the HDC2010 I2C timing is the following specifications Standard-mode or Fast-mode?

    This is related to the fall time in spec or out of spec.

  • 0 in reply to Shu-Cheng LIN
    Guru 11785 points

    Hi Sirs,

    Sorry for pushed.

    Have any update on here?

    Please let me know if still need any information.

    Thanks!!

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 91086 points

    Dear Shu-Cheng - 

    I cannot guarantee the device will work outside of the I2C spec. The advice (already given) was to either get the MCU into spec or test to your own satisfaction. 

    Seems to me that if you are running the I2C at 100kHz, you have no issue with the MCU or the spec.  

  • 0 in reply to Josh Wyatt
    Guru 11785 points

    Hi Sirs,

    Thanks for your reply.

    So, in other words is based on my description in early.

    If our system just run I2C 100k and meet I2C standard mode (100k) spec, i think no any risk on HDC2010, right?

  • 0 in reply to Shu-Cheng LIN
    TI__Guru* 91086 points

    Dear Shu-Cheng, 

    Correct. If your system supports 100kHz or 400kHz I2C SCL speeds correctly, you should be OK.