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SN74LVC1G66: Ultra Librarian software for SN74LVC1G66
Part Number: SN74LVC1G66
May I know what definition for "dt/dv input transition rise or fall time"?
We want to use a little delay in control input for the sequence require. The circuit show in below.
May I know this delay will affect the VIH or VIL threshold?
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In reply to Adam Torma:
Could you explain more about the definition for "dt/dv input transition rise or fall time"?
If we use 10kohm and 1uF filter in control pin input, may I know that will affect the control? Thanks
In reply to GaryC:
I'm sorry I didn't even realize you were referencing a spec in the datasheet. This spec is not common in signal switches and will need to do some investigating why this is here. I know that if the transition on the signal is slow that you will remain in the unknown state of the switch longer can consume more current while you are in the unknown state. That is what the app note implications of slow or floating CMOS is stating.
Being a max time I know that if you toggle signal switches fast with something >1MHz clock then you will see odd behavior on the signal path. Again with these older switches I might not get a clear answer why this spec exists but just guesses.
As far as a RC delay circuit I have simulated the delay of 10k ohm resistor and 1uF cap. There will be a longer time the signal switch stays in an unknown state and consume extra current until the voltage is in the know state above Vih and below Vil thresholds.
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