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SN74CBT3125: When OE# signal assert, the Pin A and Pin B status

user5288154
Prodigy 40 points
Part Number: SN74CBT3125

Hi sir,

    I have two question need confirm about SN74CBT3125 as bellows:

(1) When  SN74CBT3125 OE# signal assert, the Pin A and Pin B status. Does the pin A and Pin B is unstable status or tri-state？

(2)  When  SN74CBT3125 OE# signal assert, the pinA have 3.25MHZ signal , does it have risk to damage the SN74CBT3125?

Thanks

yanan

  • 0
    TI__Mastermind 45340 points

    Yanan, 

    1) When the OE pin is logic low there will be a low impedance path between A and B pins.  When OE pin is logic high there will be a high impedance path between pin A and Pin B. 

    2) The SN74CBT3125 may accept any signal from 0 to Vcc and less than <128mA if OE is logic high or logic low.

    Thank you, 

    Adam 

  • 0 in reply to Adam Torma
    Prodigy 40 points
    Hi Adam,
    It seems there have some misunderstanding about the question 1.
    When the OE pin is logic high, there will be a high impedance path between pin A and Pin B. But what the status about the Pin A or Pin B? Is it tri-state or unstable status( sometimes high and sometimes low)?

    Thanks
    yanan
  • 0 in reply to user5288154
    TI__Mastermind 45340 points
    Yanan,

    The SN74CBT3125 is a passive FET switch and doesn't have any buffering which I don't think it is 100% valid to use the term Tri-state which implies a buffered output. You will simply see Hi-Z looking into either A or B pin when the signal path is disabled.

    Thank you,
    Adam